公开(公告)号：US11522012B2

公开(公告)日：2022-12-06

申请号：US16147091

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Jack T. Kavalieros ,  Ian A. Young ,  Ram Krishnamurthy ,  Ravi Pillarisetty ,  Sasikanth Manipatruni ,  Gregory Chen ,  Hui Jae Yoo ,  Van H. Le ,  Abhishek Sharma ,  Raghavan Kumar ,  Huichu Liu ,  Phil Knag ,  Huseyin Sumbul

IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00 ,  H01L29/51

Abstract: A DIMA semiconductor structure is disclosed. The DIMA semiconductor structure includes a frontend including a semiconductor substrate, a transistor switch of a memory cell coupled to the semiconductor substrate and a computation circuit on the periphery of the frontend coupled to the semiconductor substrate. Additionally, the DIMA includes a backend that includes an RRAM component of the memory cell that is coupled to the transistor switch.

公开(公告)号：US20210089448A1

公开(公告)日：2021-03-25

申请号：US16576687

申请日：2019-09-19

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Tanay Karnik ,  Tejpal Singh ,  Yen-Cheng Liu ,  Lavanya Subramanian ,  Mahesh Kumashikar ,  Sri Harsha Chodav ,  Sreenivas Subramoney ,  Kaushik Vaidyanathan ,  Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: G06F12/0804 ,  G06F11/20 ,  G06F12/0806 ,  G06F12/0866

Abstract: Described is an low overhead method and apparatus to reconfigure a pair of buffered interconnect links to operate in one of these three modes—first mode (e.g., bandwidth mode), second mode (e.g., latency mode), and third mode (e.g., energy mode). In bandwidth mode, each link in the pair buffered interconnect links carries a unique signal from source to destination. In latency mode, both links in the pair carry the same signal from source to destination, where one link in the pair is “primary” and other is called the “assist”. Temporal alignment of transitions in this pair of buffered interconnects reduces the effective capacitance of primary, thereby reducing delay or latency. In energy mode, one link in the pair, the primary, alone carries a signal, while the other link in the pair is idle. An idle neighbor on one side reduces energy consumption of the primary.

公开(公告)号：US10777250B2

公开(公告)日：2020-09-15

申请号：US16144896

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Kaushik Vaidyanathan ,  Daniel H. Morris ,  Huichu Liu ,  Dileep J. Kurian ,  Uygar E. Avci ,  Tanay Karnik ,  Ian A. Young

IPC: G11C11/22 ,  G06F1/3234 ,  G11C11/413 ,  G11C14/00

Abstract: Embodiments include apparatuses, methods, and systems associated with save-restore circuitry including metal-ferroelectric-metal (MFM) devices. The save-restore circuitry may be coupled to a bit node and/or bit bar node of a pair of cross-coupled inverters to save the state of the bit node and/or bit bar node when an associated circuit block transitions to a sleep state, and restore the state of the bit node and/or bit bar node when the associated circuit block transitions from the sleep state to an active state. The save-restore circuitry may be used in a flip-flop circuit, a register file circuit, and/or another suitable type of circuit. The save-restore circuitry may include a transmission gate coupled between the bit node (or bit bar node) and an internal node, and an MFM device coupled between the internal node and a plate line. Other embodiments may be described and claimed.