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21.发明授权公开(公告)号：US10157005B2
公开(公告)日：2018-12-18
申请号：US15282463
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Robert C. Swanson , Tony S. Baker , Theodros Yigzaw , Chris Ackles , Celeste M. Brown
Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to utilize non-volatile random access memory for information storage in response to error conditions are disclosed. Example methods disclosed herein include accessing, with a power control unit associated with a processor, first information describing available capacities of respective reserved regions of a plurality of non-volatile memory modules, the respective reserved regions of the non-volatile memory modules being separate from respective host-visible regions of the non-volatile memory modules. Disclosed example methods also include configuring, with the power control unit, an information storage architecture based on the first information. Disclosed example methods further include storing, with the power control unit, second information in one or more of the respective reserved regions of the non-volatile memory modules in accordance with the information storage architecture.
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公开(公告)号：US09781117B2
公开(公告)日：2017-10-03
申请号：US15204799
申请日：2016-07-07
Applicant: Intel Corporation
Inventor： Robert C. Swanson , Daniel Nemiroff , Vincent J. Zimmer , Mallik Bulusu , John R. Lindsley , Robert W. Cone , Malay Trivedi , Piotr Kwidzinski
CPC classification number: H04L63/10 , G06F3/0622 , G06F3/0637 , G06F3/0683 , G06F13/28 , G06F21/554 , G06F21/57 , G06F21/572
Abstract: Embodiments of multinode hubs for trust operations are disclosed herein. In some embodiments, a multinode hub may include a plurality of memory regions, a trapping module, and a trusted platform module (TPM) component. Each memory region may be associated with and receive trust operation data from a coherent computing node. The trapping module may generate trap notifications in response to accesses to the plurality of memory regions by the associated coherent computing nodes. The trap notifications may indicate which of the plurality of memory locations has been accessed, and the TPM component may process the trust operation data in a memory region indicated by a trap notification. Other embodiments may be disclosed and/or claimed.
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公开(公告)号：US09703346B2
公开(公告)日：2017-07-11
申请号：US14312017
申请日：2014-06-23
Applicant: Intel Corporation
Inventor： Giri P. Mudusuru , Vincent J. Zimmer , Karunakara Kotary , Ronald N. Story , Robert C. Swanson , Isaac W. Oram
CPC classification number: G06F1/30 , G06F11/1441 , G06F11/2015 , G06F12/0246 , G06F12/0804 , G06F12/0866 , G06F12/0875 , G06F12/1416 , G06F12/1491 , G06F13/32 , G06F2212/1024 , G06F2212/222 , G11C5/141
Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for a Unified Extensible Firmware Interface (UEFI) with durable storage to provide memory write persistence, for example, in the event of power loss. The system may include a processor to host the firmware interface which may be configured to control access to system variables in a protected region of a volatile memory. The system may also include a power management circuit to provide power to the processor and further to provide a power loss indicator to the firmware interface. The system may also include a reserve energy storage module to provide power to the processor in response to the power loss indicator. The firmware interface is further configured to copy the system variables from the volatile memory to a non-volatile memory in response to the power loss indicator.
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公开(公告)号：US09686281B2
公开(公告)日：2017-06-20
申请号：US14938223
申请日：2015-11-11
Applicant: Intel Corporation
Inventor： Mallik Bulusu , Robert Bruce Bahnsen , Vincent J. Zimmer , Robert S. Gittins , Robert C. Swanson
CPC classification number: H04L63/0876 , G06F21/00 , H04L63/08 , H04W12/06 , H04W12/08
Abstract: An embodiment includes a secure and stable method for sending information across a compute continuum. For example, the method may include executing an application (e.g., video player) on a first node (e.g., tablet) with a desire to perform “context migration” to a second node (e.g., desktop). This may allow a user to watch a movie on the tablet, stop watching the movie, and then resume watching the movie from the desktop. To do so in a secure and stable manner, the first node may request security and performance credentials from the second node. If both credential sets satisfy thresholds, the first node may transfer content (e.g., encrypted copy of a movie) and state information (e.g., placeholder indicating where the movie was when context transfer began). The second node may then allow the user to resume his or her movie watching from the desktop. Other embodiments are described herein.
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公开(公告)号：US20160323284A1
公开(公告)日：2016-11-03
申请号：US15204799
申请日：2016-07-07
Applicant: Intel Corporation
Inventor： Robert C. Swanson , Daniel Nemiroff , Vincent J. Zimmer , Mallik Bulusu , John R. Lindsley , Robert W. Cone , Malay Trivedi , Piotr Kwidzinski
CPC classification number: H04L63/10 , G06F3/0622 , G06F3/0637 , G06F3/0683 , G06F13/28 , G06F21/554 , G06F21/57 , G06F21/572
Abstract: Embodiments of multinode hubs for trust operations are disclosed herein. In some embodiments, a multinode hub may include a plurality of memory regions, a trapping module, and a trusted platform module (TPM) component. Each memory region may be associated with and receive trust operation data from a coherent computing node. The trapping module may generate trap notifications in response to accesses to the plurality of memory regions by the associated coherent computing nodes. The trap notifications may indicate which of the plurality of memory locations has been accessed, and the TPM component may process the trust operation data in a memory region indicated by a trap notification. Other embodiments may be disclosed and/or claimed.
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Patent Agency Ranking
公开(公告)号：US20160292038A1
公开(公告)日：2016-10-06
申请号：US15178142
申请日：2016-06-09
Applicant: Intel Corporation
Inventor： Robert C. Swanson , Mariusz Oriol , Janusz Jurski , Piotr Sawicki , Robert W. Cone , William J. O'Sullivan , Mariusz Stepka , Babak Nikjou , Madhusudhan Rangarajan , Pawel Szymanski , Piotr Kwidzinski , Robert Bahnsen , Mallik Bulusu
CPC classification number: G06F11/142 , G06F1/3296 , G06F9/4881 , G06F9/5027 , G06F9/5088 , G06F11/14 , G06F11/2023 , G06F11/2028 , G06F11/203 , G06F11/2033 , G06F11/2035 , G06F11/2043 , G06F2201/805 , G06F2201/85
Abstract: Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks.
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公开(公告)号：US08751864B2
公开(公告)日：2014-06-10
申请号：US13848830
申请日：2013-03-22
Applicant: Intel Corporation
Inventor： Robert C. Swanson , Mahesh S. Natu , Rahul Khanna , Murugasamy K. Nachimuthu , Sarathy Jayakumar , Anil S. Keshavamurthy , Narayan Ranganathan
IPC: G06F11/00
CPC classification number: G06F11/203 , G06F11/1666 , G06F11/20
Abstract: In one embodiment, the present invention provides an ability to handle an error occurring during a memory migration operation in a high availability system. In addition, a method can be used to dynamically remap a memory page stored in a non-mirrored memory region of memory to a mirrored memory region. This dynamic remapping may be responsive to a determination that the memory page has been accessed more than a threshold number of times, indicating a criticality of information on the page. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明提供了处理在高可用性系统中的存储器迁移操作期间发生的错误的能力。 此外，可以使用一种方法来将存储在存储器的非镜像存储器区域中的存储器页面动态重映射到镜像存储器区域。 该动态重新映射可以响应于确定存储器页已经被访问多于阈值次数，指示页面上的信息的关键性。 描述和要求保护其他实施例。
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公开(公告)号：US10386900B2
公开(公告)日：2019-08-20
申请号：US14035534
申请日：2013-09-24
Applicant: Intel Corporation
Inventor： William R. Hannon , David P. Larsen , Robert C. Swanson
IPC: G06F1/32 , G06F1/26 , G06F1/3206 , G06F1/3287 , G06F1/329 , G06F9/48 , G06F9/50
Abstract: In an embodiment, a power management controller is to receive thread information from a scheduler, where the thread information includes thread priority information for a thread scheduled to a core of a multicore processor. The power management controller is further to receive power consumption information from a power controller and to determine a power management action to be taken by the power controller on at least one core based at least in part on the thread priority information. Other embodiments are described and claimed.
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公开(公告)号：US20190057000A1
公开(公告)日：2019-02-21
申请号：US15677325
申请日：2017-08-15
Applicant: Intel Corporation
Inventor： Kasper Wszolek , Janusz P. Jurski , Piotr Kwidzinski , Robert C. Swanson , Madhusudhan Rangarajan
IPC: G06F11/14
Abstract: Embodiments of the claimed invention include a computing device having a host processor for executing a firmware environment and a manageability controller. The firmware environment reserves a frame buffer in main memory and loads a graphics protocol driver to provide the frame buffer to an operating system of the computing device. The operating system renders graphical images to the frame buffer using a graphics driver. The manageability controller reads the graphical image from the frame buffer and may transmit the graphical image to a remote computing device. In response to a fatal error of the computing device, the manageability controller may store the graphical image to a non-volatile storage device. The host processor may assert a host reset signal in response to the fatal error, and the manageability controller may send an acknowledgment to the host processor after storing the graphical image. Other embodiments are described and claimed.
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公开(公告)号：US10073742B2
公开(公告)日：2018-09-11
申请号：US15178142
申请日：2016-06-09
Applicant: Intel Corporation
Inventor： Robert C. Swanson , Mariusz Oriol , Janusz Jurski , Piotr Sawicki , Robert W. Cone , William J. O'Sullivan , Mariusz Stepka , Babak Nikjou , Madhusudhan Rangarajan , Pawel Szymanski , Piotr Kwidzinski , Robert Bahnsen , Mallik Bulusu
CPC classification number: G06F11/142 , G06F1/3296 , G06F9/4881 , G06F9/5027 , G06F9/5088 , G06F11/14 , G06F11/2023 , G06F11/2028 , G06F11/203 , G06F11/2033 , G06F11/2035 , G06F11/2043 , G06F2201/805 , G06F2201/85
Abstract: Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks.
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