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    Dynamic configuration of input/output controller access lanes
    1.
    发明授权
    Dynamic configuration of input/output controller access lanes 有权

    公开(公告)号：US11693807B2

    公开(公告)日：2023-07-04

    申请号：US17207135

    申请日：2021-03-19

    Applicant: Intel Corporation

    Inventor： Balaji Parthasarathy ,  Ramamurthy Krithivas ,  Bradley A. Burres ,  Pawel Szymanski ,  Yi-Feng Liu

    IPC: G06F13/40 ,  G06F9/4401 ,  G06F9/445

    CPC classification number: G06F13/4027 ,  G06F9/4403 ,  G06F9/4418 ,  G06F9/44505 ,  G06F13/4022

    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.

    COMPUTING SYSTEM WITH PROTECTION AGAINST MEMORY WEAR OUT ATTACKS
    2.
    发明申请
    COMPUTING SYSTEM WITH PROTECTION AGAINST MEMORY WEAR OUT ATTACKS 审中-公开

    公开(公告)号：US20180285562A1

    公开(公告)日：2018-10-04

    申请号：US15476196

    申请日：2017-03-31

    Applicant: Intel Corporation

    Inventor： Sivakumar Radhakrishnan ,  Mahesh S. Natu ,  Pawel Szymanski ,  Zhenyu Zhu ,  Malay Trivedi ,  Kirk D. Brannock ,  Geoffrey S. Strongin

    IPC: G06F21/55 ,  G11C16/34 ,  G11C16/16 ,  G06F3/06

    Abstract: Technology for a computing system is described. The computing system can include memory, a controller, and a security management module. The controller can receive a block erase command for erasing data stored in a block of memory. The controller can store information associated with the block erase command in a store, wherein the information includes a block address associated with the data to be erased based on the block erase command. The security management module can read block addresses from the store, update a block erase count array over a defined interval to include block addresses read from the store, compare the block erase count array to a defined threshold, identify block addresses for which the block erase count array is above the defined threshold, and deny subsequent block erase commands for the identified block addresses.

    Methods and apparatus to use a security coprocessor for firmware protection
    3.
    发明授权
    Methods and apparatus to use a security coprocessor for firmware protection 有权

    公开(公告)号：US10242197B2

    公开(公告)日：2019-03-26

    申请号：US15273997

    申请日：2016-09-23

    Applicant: Intel Corporation

    Inventor： Justyna Zander ,  Marek Zmuda ,  Igor A. Tatourian ,  Pawel Szymanski

    IPC: H04L29/06 ,  G06F21/57

    Abstract: A data processing system (DPS) provides protection for firmware. The DPS comprises (a) a host module comprising a management engine and (b) a security module in communication with the host module. The security module comprises a security coprocessor and a secret identifier for the security module. The DPS also comprises at least one machine-accessible medium comprising host firmware and security firmware. The host firmware, when executed by the management engine, enables to management engine to determine whether the security module is in communication with the host module, based on the secret identifier for the security module. The security firmware, when executed by the security coprocessor, enables the security coprocessor (a) to verify integrity of the host firmware and (b) to prevent the host module from booting with the host firmware in response to a determination that the host firmware has lost integrity. Other embodiments are described and claimed.

    Dynamic configuration of input/output controller access lanes
    5.
    发明授权
    Dynamic configuration of input/output controller access lanes 有权

    公开(公告)号：US12079153B2

    公开(公告)日：2024-09-03

    申请号：US18199042

    申请日：2023-05-18

    Applicant: Intel Corporation

    Inventor： Balaji Parthasarathy ,  Ramamurthy Krithivas ,  Bradley Burres ,  Pawel Szymanski ,  Yi-Feng Liu

    IPC: G06F13/40 ,  G06F9/4401 ,  G06F9/445

    CPC classification number: G06F13/4027 ,  G06F9/4403 ,  G06F9/4418 ,  G06F9/44505 ,  G06F13/4022

    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.

    DATA TRAFFIC REDUCTION FOR REDUNDANT DATA STREAMS
    6.
    发明公开
    DATA TRAFFIC REDUCTION FOR REDUNDANT DATA STREAMS 审中-公开

    公开(公告)号：US20230412512A1

    公开(公告)日：2023-12-21

    申请号：US18038359

    申请日：2020-12-23

    Applicant: Tomasz Madajczak ,  Pawel SZYMANSKI ,  Raul DIAZ ,  Intel Corporation

    Inventor： Tomasz Madajczak ,  Pawel Szymanski ,  Raul Diaz

    IPC: H04L47/2416 ,  H04L47/12 ,  H04L49/90

    CPC classification number: H04L47/2416 ,  H04L47/12 ,  H04L49/9078

    Abstract: Systems and methods are disclosed for reducing processing for received redundant data streams. A first network controller receives a first stream of data packets and a second network controller receives a second stream of data packets redundant to the first stream. The first network controller determines, using a value of an identifier of a received packet of the first stream of data packets, that a corresponding packet of the second stream of data packets having the value of the identifier has not already been received. In response to the determining, the first network controller outputs the first data packet. The second network controller determines, using a value of an identifier of a second packet of the second stream of data packets, that the first data packet has already been received and drops the second packet in response to the determining.

    Dynamic configuration of input/output controller access lanes
    7.
    发明授权
    Dynamic configuration of input/output controller access lanes 有权

    公开(公告)号：US10956351B2

    公开(公告)日：2021-03-23

    申请号：US16566576

    申请日：2019-09-10

    Applicant: Intel Corporation

    Inventor： Balaji Parthasarathy ,  Ramamurthy Krithivas ,  Bradley Burres ,  Pawel Szymanski ,  Yi-Feng Liu

    IPC: G06F13/364 ,  G06F13/40 ,  G06F9/4401 ,  G06F9/445

    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.

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