公开(公告)号：US12175246B2

公开(公告)日：2024-12-24

申请号：US18460497

申请日：2023-09-01

Applicant: Intel Corporation

Inventor： Dan Baum ,  Michael Espig ,  James Guilford ,  Wajdi K. Feghali ,  Raanan Sade ,  Christopher J. Hughes ,  Robert Valentine ,  Bret Toll ,  Elmoustapha Ould-Ahmed-Vall ,  Mark J. Charney ,  Vinodh Gopal ,  Ronen Zohar ,  Alexander F. Heinecke

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.

公开(公告)号：US11327754B2

公开(公告)日：2022-05-10

申请号：US16366941

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Jorge Parra ,  Dan Baum ,  Robert S. Chappell ,  Michael Espig ,  Varghese George ,  Alexander Heinecke ,  Christopher Hughes ,  Subramaniam Maiyuran ,  Prasoonkumar Surti ,  Ronen Zohar ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06F9/30 ,  G06F17/11 ,  G06F7/544 ,  G06F9/38 ,  G06F7/552

Abstract: Methods and apparatus for approximation using polynomial functions are disclosed. In one embodiment, a processor comprises decoding and execution circuitry. The decoding circuitry is to decode an instruction, where the instruction comprises a first operand specifying an output location and a second operand specifying a plurality of data element values to be computed. The execution circuitry is to execute the decoded instruction. The execution includes to compute a result for each of the plurality of data element values using a polynomial function to approximate a complex function, where the computation uses coefficients stored in a lookup location for the complex function, and where data element values within different data element value ranges use different sets of coefficients. The execution further includes to store results of the computation in the output location.

公开(公告)号：US10896043B2

公开(公告)日：2021-01-19

申请号：US16146854

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Bret Toll ,  Alexander F. Heinecke ,  Christopher J. Hughes ,  Ronen Zohar ,  Michael Espig ,  Dan Baum ,  Raanan Sade ,  Robert Valentine ,  Mark J. Charney ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06F17/16 ,  G06F12/02 ,  G06F9/30 ,  G06F12/06 ,  G06F9/38 ,  G06T1/20 ,  G06F12/0897 ,  G06F12/0875 ,  G06F9/345

Abstract: Disclosed embodiments relate to instructions for fast element unpacking. In one example, a processor includes fetch circuitry to fetch an instruction whose format includes fields to specify an opcode and locations of an Array-of-Structures (AOS) source matrix and one or more Structure of Arrays (SOA) destination matrices, wherein: the specified opcode calls for unpacking elements of the specified AOS source matrix into the specified Structure of Arrays (SOA) destination matrices, the AOS source matrix is to contain N structures each containing K elements of different types, with same-typed elements in consecutive structures separated by a stride, the SOA destination matrices together contain K segregated groups, each containing N same-typed elements, decode circuitry to decode the fetched instruction, and execution circuitry, responsive to the decoded instruction, to unpack each element of the specified AOS matrix into one of the K element types of the one or more SOA matrices.

公开(公告)号：US10782971B1

公开(公告)日：2020-09-22

申请号：US16370922

申请日：2019-03-30

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  ElMoustapha Ould-Ahmed-Vall ,  Jorge E. Parra ,  Prasoonkumar Surti ,  Krishna N. Vinod ,  Ronen Zohar

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/345

Abstract: Methods and apparatus for vector-matrix comparison are disclosed. In one embodiment, a processor comprises decoding and execution circuitry. The decoding circuitry decodes an instruction, where operands of the instruction specifies an output location to store output results, a vector of data element values, and a matrix of data element values. The execution circuitry executes the decoded instruction. The execution includes to map each of the data element values of the vector to one of consecutive rows of the matrix; for each data element value of the vector, to compare that data element value of the vector with data element values in a respective row of the matrix and obtain data element match results. The execution further includes to store the output results based on the data element match results, where each output result maps to a respective data element column position and indicates a vector match result.

公开(公告)号：US10719323B2

公开(公告)日：2020-07-21

申请号：US16144902

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Dan Baum ,  Michael Espig ,  James Guilford ,  Wajdi K. Feghali ,  Raanan Sade ,  Christopher J. Hughes ,  Robert Valentine ,  Bret Toll ,  Elmoustapha Ould-Ahmed-Vall ,  Mark J. Charney ,  Vinodh Gopal ,  Ronen Zohar ,  Alexander F. Heinecke

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.

公开(公告)号：US20170364476A1

公开(公告)日：2017-12-21

申请号：US15640395

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Ronen Zohar ,  Mark Seconi ,  Rajesh Parthasarathy ,  Srinivas Chennupaty ,  Mark Buxton ,  Chuck Desylva ,  Mohammad Abdallah

IPC: G06F17/10 ,  G06F7/48 ,  G06F7/544 ,  G06F9/30

CPC classification number: G06F17/10 ,  G06F7/48 ,  G06F7/5443 ,  G06F9/3001

Abstract: Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.

公开(公告)号：US20170220347A1

公开(公告)日：2017-08-03

申请号：US15485356

申请日：2017-04-12

Applicant: Intel Corporation

Inventor： Ronen Zohar ,  Shane Story

IPC: G06F9/30 ,  G06F17/10

CPC classification number: G06F9/30014 ,  G06F7/49947 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30185 ,  G06F17/10

Abstract: In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.

公开(公告)号：US20170161068A1

公开(公告)日：2017-06-08

申请号：US15345221

申请日：2016-11-07

Applicant: Intel Corporation

Inventor： Rajiv Kapoor ,  Ronen Zohar ,  Mark Buxton ,  Zeev Sperber ,  Koby Gottlieb

IPC: G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/30021 ,  G06F7/026 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/3887 ,  G06F12/0875 ,  G06F2212/452

Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

公开(公告)号：US20160139918A1

公开(公告)日：2016-05-19

申请号：US15003951

申请日：2016-01-22

Applicant: Intel Corporation

Inventor： Ronen Zohar ,  Shane Story

IPC: G06F9/30

CPC classification number: G06F9/30014 ,  G06F7/49947 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30185 ,  G06F17/10

Abstract: In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在处理器中接收舍入指令和立即值的方法，确定立即值的舍入模式超驰指示符是否是活动的，并且如果这样执行对源操作数的舍入操作 处理器的浮点单元响应于舍入指令，并根据立即操作数中列出的舍入模式。 描述和要求保护其他实施例。

公开(公告)号：US20150212816A1

公开(公告)日：2015-07-30

申请号：US14684412

申请日：2015-04-12

Applicant: Intel Corporation

Inventor： Rajiv Kapoor ,  Ronen Zohar ,  Mark Buxton ,  Zeev Sperber ,  Koby Gottlieb

IPC: G06F9/30

CPC classification number: G06F9/30021 ,  G06F7/026 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/3887 ,  G06F12/0875 ,  G06F2212/452

Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

Abstract translation: 一种用于在处理器中包括用于对打包或未打包的数据执行逻辑比较和分支支持操作的指令的方法和装置。 在一个实施例中，指令解码逻辑解码用于执行单元对包括逻辑比较的打包数据元素进行操作的指令。 包括128位打包数据寄存器的寄存器文件存储打包的单精度浮点数（SPFP）和压缩整数数据元素。 逻辑比较可以包括SPFP数据元素的比较和整数数据元素的比较，并且设置至少一个位以指示结果。 基于这些比较，采取分支支持行动。 这种分支支持动作可以包括设置至少一个比特，响应于分支指令又可以由分支单元利用该比特。 或者，分支支持动作可以包括分支到指示的目标代码位置。