公开(公告)号：US20160170883A1

公开(公告)日：2016-06-16

申请号：US14567602

申请日：2014-12-11

Applicant: Intel Corporation

Inventor： Ruchira Sasanka ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F9/30043 ,  G06F12/0804 ,  G06F12/0875 ,  G06F12/0886 ,  G06F2212/283 ,  G06F2212/452

Abstract: In one embodiment of the invention, a processor comprising an upper level cache and at least one processor core. The at least one processor core includes one or more registers and a plurality of instruction processing stages: a decode unit to decode an instruction requiring an input of a plurality of data elements, wherein a size of each of the plurality of data elements is less than a cache line size of the processor; an execution unit to load the plurality of data elements to the one or more registers of the processor, without loading data elements spatially adjacent to the plurality of data elements or the plurality of data elements in an upper level cache.

Abstract translation: 在本发明的一个实施例中，处理器包括上级缓存和至少一个处理器核心。 所述至少一个处理器核心包括一个或多个寄存器和多个指令处理阶段：解码单元，用于解码需要输入多个数据元素的指令，其中所述多个数据元素中的每一个的大小小于 处理器的高速缓存行大小; 执行单元，用于将多个数据元素加载到处理器的一个或多个寄存器，而不将空间上与多个数据元素或多个数据元素空间相邻的数据元素加载到高级缓存中。

公开(公告)号：US09256276B2

公开(公告)日：2016-02-09

申请号：US14039368

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Ruchira Sasanka ,  Alexander Gendler ,  Udi Sherel

IPC: G06F1/32 ,  G06F12/02

CPC classification number: G06F1/3296 ,  G06F1/266 ,  G06F1/324 ,  G06F12/0223 ,  G06F12/084 ,  G06F2212/62 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: In an embodiment, a processor includes one or more cores including a first core operable at an operating voltage between a minimum operating voltage and a maximum operating voltage. The processor also includes a power control unit including first logic to enable coupling of ancillary logic to the first core responsive to the operating voltage being less than or equal to a threshold voltage, and to disable the coupling of the ancillary logic to the first core responsive to the operating voltage being greater than the threshold voltage. Other embodiments are described and claimed.

公开(公告)号：US10725755B2

公开(公告)日：2020-07-28

申请号：US15615798

申请日：2017-06-06

Applicant: Intel Corporation

Inventor： David J. Sager ,  Ruchira Sasanka ,  Ron Gabor ,  Shlomo Raikin ,  Joseph Nuzman ,  Leeor Peled ,  Jason A. Domer ,  Ho-Seop Kim ,  Youfeng Wu ,  Koichi Yamada ,  Tin-Fook Ngai ,  Howard H. Chen ,  Jayaram Bobba ,  Jeffrey J. Cook ,  Omar M. Shaikh ,  Suresh Srinivas

IPC: G06F8/41 ,  G06F9/38 ,  G06F9/54 ,  G06F11/36

Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

公开(公告)号：US10684833B2

公开(公告)日：2020-06-16

申请号：US15921813

申请日：2018-03-15

Applicant: Intel Corporation

Inventor： Ruchira Sasanka ,  Karthik Raman ,  Konstantinos Krommydas

IPC: G06F8/41 ,  G06F9/38

Abstract: An embodiment of a semiconductor package apparatus may include technology to identify a nested loop in a set of executable instructions, and determine at runtime if the nested loop is a candidate for cache blocking. Other embodiments are disclosed and claimed.

公开(公告)号：US10379827B2

公开(公告)日：2019-08-13

申请号：US15393931

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Ruchira Sasanka

IPC: G06F8/41 ,  G06F9/30 ,  G06F11/34 ,  G06F9/455

Abstract: Techniques are disclosed to identify a frequently-executed region of code during runtime execution of the code, generate initial profiling code for the frequently-executed region of code, cause the initial profiling code to be executed for a minimum number of processing cycles of the computer, and identify replacement candidate store instruction(s) that store a value that is not read by the frequently-executed region of code during execution of the initial profiling code. Replacement candidate load instruction(s) may also be identified that load a value that is not stored or loaded by the frequently-executed region of code during execution of the initial profiling code. Optimized code for the frequently-executed region of code may be generated by replacing each of the replacement candidate store or load instructions(s) with a non-temporal store or load instruction. The optimized code may be executed instead of the frequently-executed region of code during subsequent runtime execution.

公开(公告)号：US20190095335A1

公开(公告)日：2019-03-28

申请号：US16203847

申请日：2018-11-29

Applicant: INTEL CORPORATION

Inventor： Ruchira Sasanka

IPC: G06F12/0864 ,  G06F12/0811 ,  G06F12/0808 ,  G06F12/128

Abstract: A processor includes a processor core and a cache controller coupled to the processor core. The cache controller is to allocate, for a memory, a plurality of cache entries in a cache, wherein the processor core is to: detect an amount of the memory installed in a computing system and, responsive to detecting less than a maximum allowable amount of the memory for the computing system, direct the cache controller to increase a number of ways of the cache in which to allocate the plurality of cache entries.

公开(公告)号：US20160085675A1

公开(公告)日：2016-03-24

申请号：US14933378

申请日：2015-11-05

Applicant: Intel Corporation

Inventor： Ruchira Sasanka ,  Alexander Gendler ,  Udi Sherel

IPC: G06F12/08 ,  G06F1/26

CPC classification number: G06F1/3296 ,  G06F1/266 ,  G06F1/324 ,  G06F12/0223 ,  G06F12/084 ,  G06F2212/62 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: In an embodiment, a processor includes one or more cores including a first core operable at an operating voltage between a minimum operating voltage and a maximum operating voltage. The processor also includes a power control unit including first logic to enable coupling of ancillary logic to the first core responsive to the operating voltage being less than or equal to a threshold voltage, and to disable the coupling of the ancillary logic to the first core responsive to the operating voltage being greater than the threshold voltage. Other embodiments are described and claimed.