公开(公告)号：US20170371565A1

公开(公告)日：2017-12-28

申请号：US15195452

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Han Liu ,  Shantanu R. Rajwade ,  Pranav Kalavade

IPC: G06F3/06 ,  G11C11/56

CPC classification number: G06F3/0613 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G11C7/06 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/32

Abstract: In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to receive a read request from a computing host; identify a plurality of pages specified by the read request that are stored in the same group of memory cells of the NAND flash memory, wherein each memory cell of the group of memory cells is to store a bit of each of the plurality of identified pages; and read, in a single read cycle, the plurality of pages from the group of memory cells of the NAND flash memory.

公开(公告)号：US09792997B2

公开(公告)日：2017-10-17

申请号：US15183582

申请日：2016-06-15

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Neal R. Mielke ,  Krishna K. Parat ,  Shyam Sunder Raghunathan

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10

Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.

公开(公告)号：US09703494B1

公开(公告)日：2017-07-11

申请号：US15276080

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade

IPC: G11C7/10 ,  G06F3/06 ,  G11C11/56 ,  G11C16/34 ,  G06F11/10 ,  G11C29/52

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621 ,  G11C2211/5648

Abstract: In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to store a first page of data in a plurality of cells of the NAND flash memory in a first programming pass; and preserve the readability of the first page of data in the plurality of cells during a subsequent programming pass comprising a plurality of program loops, at least one of the plurality of program loops to comprise application of a first voltage to a first group of cells of the plurality of cells and application of a second voltage to a second group of cells of the plurality of cells, wherein the first group comprises cells that were not programmed in the first programming pass and the second group comprises cells that were programmed in the first programming pass.