公开(公告)号：US20220207154A1

公开(公告)日：2022-06-30

申请号：US17134333

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Richard Winterton ,  Mohammad Reza Haghighat ,  Asit Mallick ,  Alaa Alameldeen ,  Abhishek Basak ,  Jason W. Brandt ,  Michael Chynoweth ,  Carlos Rozas ,  Scott Constable ,  Martin Dixon ,  Matthew Fernandez ,  Fangfei Liu ,  Francis McKeen ,  Joseph Nuzman ,  Gilles Pokam ,  Thomas Unterluggauer ,  Xiang Zou

IPC: G06F21/60 ,  H04L9/08 ,  H04L9/30

Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a hybrid key generator and memory protection hardware. The hybrid key generator is to generate a hybrid key based on a public key and multiple process identifiers. Each of the process identifiers corresponds to one or more memory spaces in a memory. The memory protection hardware is to use the first hybrid key to protect to the memory spaces.

公开(公告)号：US20220207148A1

公开(公告)日：2022-06-30

申请号：US17134345

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Carlos Rozas ,  Fangfei Liu ,  Xiang Zou ,  Francis McKeen ,  Jason W. Brandt ,  Joseph Nuzman ,  Alaa Alameldeen ,  Abhishek Basak ,  Scott Constable ,  Thomas Unterluggauer ,  Asit Mallick ,  Matthew Fernandez

IPC: G06F21/57 ,  G06F9/38 ,  G06F21/54

Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and branch circuitry coupled to the decode circuitry. The decode circuitry is to decode a branch hardening instruction to mitigate vulnerability to a speculative execution attack. The branch circuitry is to be hardened in response to the branch hardening instruction.

公开(公告)号：US20220207146A1

公开(公告)日：2022-06-30

申请号：US17134341

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Carlos Rozas ,  Fangfei Liu ,  Xiang Zou ,  Francis McKeen ,  Jason W. Brandt ,  Joseph Nuzman ,  Alaa Alameldeen ,  Abhishek Basak ,  Scott Constable ,  Thomas Unterluggauer ,  Asit Mallick ,  Matthew Fernandez

IPC: G06F21/57 ,  G06F9/38 ,  G06F21/54

Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and load circuitry coupled to the decode circuitry. The decode circuitry is to decode a load hardening instruction to mitigate vulnerability to a speculative execution attack. The load circuitry is to be hardened in response to the load hardening instruction.

公开(公告)号：US09971615B2

公开(公告)日：2018-05-15

申请号：US13836628

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Gilbert Neiger ,  Richard Uhlig ,  Xiang Zou ,  Lawrence Smith, III ,  Scott Rodgers

IPC: G06F9/46 ,  G06F9/455

CPC classification number: G06F9/45533 ,  G06F9/45558 ,  G06F2009/45583

Abstract: In one embodiment, a predefined behavior of a virtual machine monitor (VMM) with respect to one or more virtual machines (VMs) is identified, and processor-managed resources associated with the one or more VMs are utilized based on the predefined behavior of the VMM.

公开(公告)号：US20170102944A1

公开(公告)日：2017-04-13

申请号：US15386615

申请日：2016-12-21

Applicant: Intel Corporation

Inventor： Gautham Chinya ,  Hong Wang ,  Prashant Sethi ,  Shivnandan Kaushik ,  Bryant Bigbee ,  John Shen ,  Richard Hankins ,  Xiang Zou ,  Baiju V. Patel ,  Jason W. Brandt ,  Anil Aggarwal ,  John L. Reid

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F9/3005 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/461

Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.

公开(公告)号：US09063804B2

公开(公告)日：2015-06-23

申请号：US14036768

申请日：2013-09-25

Applicant: INTEL CORPORATION

Inventor： Chris J. Newburn ,  Robert P. Knight ,  Robert Y. Geva ,  Dion Rodgers ,  Xiang Zou ,  Hong Wang ,  Bryant E. Bigbee ,  Ittai Anati

IPC: G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/54 ,  G06F11/34 ,  G06F11/36

CPC classification number: G06F9/542 ,  G06F11/348 ,  G06F11/3612 ,  G06F2201/86 ,  G06F2201/885

Abstract: Method, apparatus, and system for monitoring performance within a processing resource, which may be used to modify user-level software. Some embodiments of the invention pertain to an architecture to allow a user to improve software running on a processing resources on a per-thread basis in real-time and without incurring significant processing overhead.

Abstract translation: 用于监控处理资源内的性能的方法，装置和系统，其可用于修改用户级软件。 本发明的一些实施例涉及允许用户实时地在每个线程的基础上改进在处理资源上运行的软件并且不产生显着的处理开销的架构。

公开(公告)号：US11748649B2

公开(公告)日：2023-09-05

申请号：US16714644

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Xiang Zou ,  Justin Hogaboam ,  Adam Holmes ,  Sonika Johri

IPC: G06N10/00 ,  G06F9/22 ,  G06N10/40

CPC classification number: G06N10/00 ,  G06F9/223 ,  G06N10/40

Abstract: Apparatus and method for specifying quantum operation parallelism. For example, one embodiment of an apparatus comprises: instruction fetch circuitry to fetch a plurality of quantum instructions from a memory or a cache; slice-based instruction processing circuitry to identify quantum circuit slices comprising sets of one or more of the plurality of quantum instructions; and one or more instruction decoders to decode the quantum instructions to generate quantum microoperations; and quantum execution circuitry to execute sets of the quantum microoperations in parallel based on the quantum circuit slices.

公开(公告)号：US11599818B2

公开(公告)日：2023-03-07

申请号：US16714663

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Xiang Zou ,  Shavindra Premaratne

IPC: G06N10/00

Abstract: Apparatus and method for performing a quantum rotation operation. For example, one embodiment of an apparatus comprises: a decoder to decode a plurality of instructions; execution circuitry to execute a first instruction or first set of the instructions to generate a floating point (FP) value and to store the FP value in a first register; the execution circuitry to execute a second instruction or second set of the one or more of the instructions to read the FP value from the first register and compress the FP value to generate a compressed FP value having a precision selected for performing quantum rotation operations; and quantum interface circuitry to process the compressed FP value to cause a quantum rotation to be performed on one or more qubits of a quantum processor.

公开(公告)号：US20220207138A1

公开(公告)日：2022-06-30

申请号：US17134350

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Carlos Rozas ,  Fangfei Liu ,  Xiang Zou ,  Francis McKeen ,  Jason W. Brandt ,  Joseph Nuzman ,  Alaa Alameldeen ,  Abhishek Basak ,  Scott Constable ,  Thomas Unterluggauer ,  Asit Mallick ,  Matthew Fernandez

IPC: G06F21/55 ,  G06F21/54 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a decode circuitry and store circuitry coupled to the decode circuitry. The decode circuitry is to decode a store hardening instruction to mitigate vulnerability to a speculative execution attack. The store circuitry is to be hardened in response to the store hardening instruction.