公开(公告)号：US11645135B2

公开(公告)日：2023-05-09

申请号：US17020663

申请日：2020-09-14

Applicant: Intel Corporation

Inventor： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

IPC: G06F11/07 ,  G06F12/00 ,  G06F9/38 ,  G06F12/109 ,  G06F21/60 ,  G06F12/14

CPC classification number: G06F11/0751 ,  G06F9/38 ,  G06F11/073 ,  G06F12/00 ,  G06F12/109 ,  G06F21/60 ,  G06F12/145 ,  G06F2212/1032 ,  G06F2212/1052 ,  G06F2212/656

Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

公开(公告)号：US10776190B2

公开(公告)日：2020-09-15

申请号：US16224579

申请日：2018-12-18

Applicant: Intel Corporation

Inventor： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

IPC: G06F11/00 ,  G06F11/07 ,  G06F12/00 ,  G06F9/38 ,  G06F12/109 ,  G06F21/60 ,  G06F12/14

Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

公开(公告)号：US10162694B2

公开(公告)日：2018-12-25

申请号：US14977354

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

IPC: G06F11/00 ,  G06F11/07 ,  G06F12/00 ,  G06F9/38

Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

公开(公告)号：US20150213269A1

公开(公告)日：2015-07-30

申请号：US14679145

申请日：2015-04-06

Applicant: Intel Corporation

Inventor： Vincent J. Zimmer ,  Bryant E. Bigbee ,  Andrew J. Fish ,  Mark S. Doran

IPC: G06F21/57 ,  G06F9/44

CPC classification number: G06F21/57 ,  G06F9/4401 ,  G06F9/4406 ,  G06F9/4416 ,  G06F21/575 ,  G06F2221/034

Abstract: In one embodiment, the present invention includes a method to establish a secure pre-boot environment in a computer system and performs at least one secure operation in the secure environment. In one embodiment, the secure operation may be storage of a secret in the secure pre-boot environment.

Abstract translation: 在一个实施例中，本发明包括在计算机系统中建立安全预引导环境并在安全环境中执行至少一个安全操作的方法。 在一个实施例中，安全操作可以是安全预引导环境中的秘密的存储。

公开(公告)号：US09063804B2

公开(公告)日：2015-06-23

申请号：US14036768

申请日：2013-09-25

Applicant: INTEL CORPORATION

Inventor： Chris J. Newburn ,  Robert P. Knight ,  Robert Y. Geva ,  Dion Rodgers ,  Xiang Zou ,  Hong Wang ,  Bryant E. Bigbee ,  Ittai Anati

IPC: G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/54 ,  G06F11/34 ,  G06F11/36

CPC classification number: G06F9/542 ,  G06F11/348 ,  G06F11/3612 ,  G06F2201/86 ,  G06F2201/885

Abstract: Method, apparatus, and system for monitoring performance within a processing resource, which may be used to modify user-level software. Some embodiments of the invention pertain to an architecture to allow a user to improve software running on a processing resources on a per-thread basis in real-time and without incurring significant processing overhead.

Abstract translation: 用于监控处理资源内的性能的方法，装置和系统，其可用于修改用户级软件。 本发明的一些实施例涉及允许用户实时地在每个线程的基础上改进在处理资源上运行的软件并且不产生显着的处理开销的架构。

公开(公告)号：US10452403B2

公开(公告)日：2019-10-22

申请号：US14866875

申请日：2015-09-26

Applicant: Intel Corporation

Inventor： Hong Wang ,  John P. Shen ,  Edward T. Grochowski ,  Richard A. Hankins ,  Gautham N. Chinya ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik ,  Xiang Chris Zou ,  Per Hammarlund ,  Scott Dion Rodgers ,  Xinmin Tian ,  Anil Aggawal ,  Prashant Sethi ,  Baiju V. Patel ,  James P Held

IPC: G06F9/455 ,  G06F9/38 ,  G06F9/30 ,  G06F9/48

Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

公开(公告)号：US20230273846A1

公开(公告)日：2023-08-31

申请号：US18313905

申请日：2023-05-08

Applicant: Intel Corporation

Inventor： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

IPC: G06F11/07 ,  G06F12/00 ,  G06F9/38 ,  G06F12/109 ,  G06F21/60

CPC classification number: G06F11/0751 ,  G06F11/073 ,  G06F12/00 ,  G06F9/38 ,  G06F12/109 ,  G06F21/60 ,  G06F12/145

Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

公开(公告)号：US20190235948A1

公开(公告)日：2019-08-01

申请号：US16224579

申请日：2018-12-18

Applicant: Intel Corporation

Inventor： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

IPC: G06F11/07 ,  G06F12/109 ,  G06F9/38 ,  G06F12/00

CPC classification number: G06F11/0751 ,  G06F9/38 ,  G06F11/073 ,  G06F12/00 ,  G06F12/109 ,  G06F12/145 ,  G06F21/60 ,  G06F2212/1032 ,  G06F2212/1052 ,  G06F2212/656

Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

公开(公告)号：US20170010895A1

公开(公告)日：2017-01-12

申请号：US15276290

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Hong Wang ,  John P. Shen ,  Edward T. Grochowski ,  Richard A. Hankins ,  Gautham N. Chinya ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik ,  Xiang Chris Zou ,  Per Hammarlund ,  Scott Dion Rodgers ,  Xinmin Tian ,  Anil Aggarwal ,  Prashant Sethi ,  Baiju V. Patel ,  James P. Held

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48

CPC classification number: G06F9/3867 ,  G06F9/30003 ,  G06F9/30043 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3851 ,  G06F9/4843 ,  G06F9/4881

Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

Abstract translation: 在一个实施例中，提供了一种方法。 该方法包括响应于在应用级程序的控制下对第二指令定序器执行用户级指令来管理第一指令定序器上的用户级线程。 在第二指令定序器上运行第一用户级线程并且包含一个或多个用户级指令。 第一用户级指令至少具有1）引用一个或多个指令定序器的字段，或者2）使用指向代码执行代码时特定寻址一个或多个指令定序器的代码的指针进行隐式引用。

公开(公告)号：US20210141683A1

公开(公告)日：2021-05-13

申请号：US17020663

申请日：2020-09-14

Applicant: Intel Corporation

Inventor： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

IPC: G06F11/07 ,  G06F12/00 ,  G06F9/38 ,  G06F12/109 ,  G06F21/60

Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.