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公开(公告)号：US20190391329A1
公开(公告)日：2019-12-26
申请号：US16270886
申请日：2019-02-08
Applicant: International Business Machines Corporation
Inventor： Yves Martin , Jason S. Orcutt , Tymon Barwicz , William Green
Abstract: Techniques are provided for single edge coupling of chips with integrated waveguides. For example, a package structure includes a first chip with a first critical edge, and a second chip with a second critical edge. The first and second chips include integrated waveguides with end portions that terminate on the first and second critical edges. The second chip includes a signal reflection structure that is configured to reflect an optical signal propagating in one or more of the integrated waveguides of the second chip. The first and second chips are edge-coupled at the first and second critical edges such that the end portions of the integrated waveguides of the first and second chips are aligned to each other, and wherein all signal input/output between the first and second chips occurs at the single edge-coupled interface.
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公开(公告)号：US20170146754A1
公开(公告)日：2017-05-25
申请号：US15333847
申请日：2016-10-25
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Tymon Barwicz , Yves Martin
CPC classification number: G02B6/4232 , G02B6/12002 , G02B6/12004 , H01L2224/83192 , H01S5/0224 , H01S5/02268 , H01S5/02272 , H01S5/02469
Abstract: A technique relates to assembling a multi-chip system. A first chip stack element having two major surfaces and a first solder pad, a first vertical stop, a first lateral stop and a first waveguiding element is provided. A second chip stack element having two major surfaces and including a second solder pad, a flow resistor connected to the second solder pad, a second vertical stop, a second lateral stop, a reservoir pad connected to the flow resistor, and a second waveguiding element is provided. A solder material is plated to form a plated solder pad. A technique includes pre-aligning the first chip stack element and the second chip stack element, raising the temperature to a temperature above the melting temperature of the solder material, and flowing solder through the flow resistor. Aspects include aligning the first and second waveguiding elements and cooling the connected assembly to re-solidify the solder material.
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公开(公告)号：US20250148328A1
公开(公告)日：2025-05-08
申请号：US18387033
申请日：2023-11-04
Applicant: International Business Machines Corporation
Inventor： Russell A. Budd , Eric Zhang , Jared Barney Hertzberg , Jason S. Orcutt , Sami Rosenblatt , James B Hannon , Yves Martin , Bucknell C. Webb
Abstract: A method comprises performing a pattern recognition process to determine a geometry of a superconducting quantum device comprising one or more Josephson junctions, determining, based on the geometry determined by the pattern recognition process, a laser beam illumination pattern for laser annealing the one or more Josephson junctions of the superconducting quantum device, and configuring a laser microscope to generate the laser beam illumination pattern.
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公开(公告)号：US20220293844A1
公开(公告)日：2022-09-15
申请号：US17198666
申请日：2021-03-11
Applicant: International Business Machines Corporation
Inventor： Yves Martin , Jason S. Orcutt , Antoine Hervier , Martin O. Sandberg , Harry Jonathon Mamin
Abstract: Circuits and methods of operation that can facilitate reducing surface losses for quantum devices are provided. In one example, a quantum device can comprise a dielectric layer, a first electrode, and a second electrode. The dielectric layer can comprise a recess formed in a surface of the dielectric layer that reduces a thickness of the dielectric layer from a first thickness external to a footprint of the recess to a second thickness within the footprint of the recess. The second thickness can be less than the first thickness. The first electrode can be positioned within the footprint of the recess. The second electrode can be electrically isolated from the first electrode by the dielectric layer. The first and second electrodes can be positioned on opposing surfaces of the dielectric layer.
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公开(公告)号：US11289638B2
公开(公告)日：2022-03-29
申请号：US16908704
申请日：2020-06-22
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Douglas Max Gill , Martin O. Sandberg , Vivekananda P. Adiga , Yves Martin , Hanhee Paik
Abstract: A method for improving lifetime and coherence time of a qubit in a quantum mechanical device is provided. The method includes providing a substrate having a frontside and a backside, the frontside having at least one qubit formed thereon, the at least one qubit having capacitor pads. The method further includes at least one of removing an amount of substrate material from the backside of the substrate at an area opposite the at least one qubit or depositing a superconducting metal layer at the backside of the substrate at the area opposite the at least one qubit to reduce radiofrequency electrical current loss due to at least one of silicon-air (SA) interface, metal-air (MA) interface or silicon-metal (SM) interface so as to enhance a lifetime (T1) and a coherence time (T2) in the at least one qubit.
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Patent Agency Ranking
公开(公告)号：US11166381B2
公开(公告)日：2021-11-02
申请号：US16140883
申请日：2018-09-25
Applicant: International Business Machines Corporation
Inventor： Yves Martin , Tymon Barwicz
Abstract: Solder-pinning metal pads for electronic components and techniques for use thereof to mitigate de-wetting are provided. In one aspect, a structure includes: a substrate; and a solder pad on the substrate, wherein the solder pad has sidewalls extending up from a surface thereof. For instance, the sidewalls can be present at edges of the solder pad, or inset from the edges of the solder pad. The sidewalls can be vertical or extend up from the solder pad at an angle. The sidewalls can be formed from the same material or a different material as the solder pad. A method is also provided that includes forming a solder pad on a substrate, the solder pad comprising sidewalls extending up from a surface thereof.
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公开(公告)号：US10935533B2
公开(公告)日：2021-03-02
申请号：US15869641
申请日：2018-01-12
Applicant: International Business Machines Corporation
Inventor： Josephine B Chang , Yves Martin , Theodore G. Van Kessel
Abstract: A gas sensor enclosure is provided. The gas sensor enclosure includes at least two coaxial shells, a gas sensor, a gas permeable membrane that exposes a portion of the gas sensor to gas exchange through one of the at least two coaxial shells and a screen. The screen encloses the at least two coaxial shells, the gas sensor and the gas permeable membrane.
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公开(公告)号：US10901146B2
公开(公告)日：2021-01-26
申请号：US16445623
申请日：2019-06-19
Applicant: International Business Machines Corporation
Inventor： Yves Martin , Jason S. Orcutt , Tymon Barwicz , William Green
Abstract: Techniques are provided for single edge coupling of chips with integrated waveguides. For example, a package structure includes a first chip with a first critical edge, and a second chip with a second critical edge. The first and second chips include integrated waveguides with end portions that terminate on the first and second critical edges. The second chip includes a signal reflection structure that is configured to reflect an optical signal propagating in one or more of the integrated waveguides of the second chip. The first and second chips are edge-coupled at the first and second critical edges such that the end portions of the integrated waveguides of the first and second chips are aligned to each other, and wherein all signal input/output between the first and second chips occurs at the single edge-coupled interface.
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公开(公告)号：US10393962B2
公开(公告)日：2019-08-27
申请号：US15827306
申请日：2017-11-30
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Tymon Barwicz , Yves Martin , Jae-Woong Nah
Abstract: A method for assembling a semiconductor device includes: receiving a first chip including a plurality of first bonding pads, a first standoff and a second standoff, wherein a first solder is deposited on each of the first bonding pads; depositing a second solder on each of the first and second standoffs; arranging a second chip over the first chip, wherein the second chip includes a plurality of second bonding pads, and at least one of the second bonding pads has a corresponding first bonding pad; heating the second chip over a melting point of the second solder to melt the second solder, and placing the second chip on the first chip to touch and solidify the second solder on each of the first and second standoffs; performing a reflow process to melt the first solder on each of the first bonding pads so that at least one of the first solders touches a corresponding second bonding pad; and waiting a predetermined period of time to allow the second chip to move until a side edge of the second chip touches a waveguide of the first chip.
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公开(公告)号：US10302859B1
公开(公告)日：2019-05-28
申请号：US16015884
申请日：2018-06-22
Applicant: International Business Machines Corporation
Inventor： Yves Martin , Jason S. Orcutt , Tymon Barwicz , William Green
Abstract: Techniques are provided for single edge coupling of chips with integrated waveguides. For example, a package structure includes a first chip with a first critical edge, and a second chip with a second critical edge. The first and second chips include integrated waveguides with end portions that terminate on the first and second critical edges. The second chip includes a signal reflection structure that is configured to reflect an optical signal propagating in one or more of the integrated waveguides of the second chip. The first and second chips are edge-coupled at the first and second critical edges such that the end portions of the integrated waveguides of the first and second chips are aligned to each other, and wherein all signal input/output between the first and second chips occurs at the single edge-coupled interface.
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