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    INTERCONNECT CHIP AND L-COUPLER FOR MODULAR QUANTUM LINKS
    1.
    发明申请
    INTERCONNECT CHIP AND L-COUPLER FOR MODULAR QUANTUM LINKS 有权

    公开(公告)号：US20240412090A1

    公开(公告)日：2024-12-12

    申请号：US18330680

    申请日：2023-06-07

    Applicant: International Business Machines Corporation

    Inventor： Neereja Sundaresan ,  Shawn Anthony Hall ,  Jason S. Orcutt ,  Jae-Woong Nah ,  Yves Martin ,  Wen-Sen Lu ,  John Michael Cotte

    IPC: G06N10/40

    Abstract: Systems and techniques that facilitate coupling a superconducting cable to a interconnect chip and a quantum processor. In various embodiments, a system can comprise a quantum processor, one or more interconnect chips, and one or more cable connections. The quantum processor can comprise a plurality of qubits. Additionally, the one or more interconnect chips can be bonded to the quantum processor, and the one or more cable connections can be coupled to the one or more interconnect chips. With embodiments, the one or more interconnect chips can comprise one or more signal routings from the one or more cable connections to the quantum processor. Further, in embodiments, a first signal can pass from the one or more cable connections to at least one of the plurality of qubits.

    Quantum device with low surface losses
    2.
    发明授权
    Quantum device with low surface losses 有权

    公开(公告)号：US11621387B2

    公开(公告)日：2023-04-04

    申请号：US17198666

    申请日：2021-03-11

    Applicant: International Business Machines Corporation

    Inventor： Yves Martin ,  Jason S. Orcutt ,  Antoine Hervier ,  Martin O. Sandberg ,  Harry Jonathon Mamin

    IPC: H01L39/22 ,  H01L29/66 ,  H01L39/02 ,  H01L39/24

    Abstract: Circuits and methods of operation that can facilitate reducing surface losses for quantum devices are provided. In one example, a quantum device can comprise a dielectric layer, a first electrode, and a second electrode. The dielectric layer can comprise a recess formed in a surface of the dielectric layer that reduces a thickness of the dielectric layer from a first thickness external to a footprint of the recess to a second thickness within the footprint of the recess. The second thickness can be less than the first thickness. The first electrode can be positioned within the footprint of the recess. The second electrode can be electrically isolated from the first electrode by the dielectric layer. The first and second electrodes can be positioned on opposing surfaces of the dielectric layer.

    HOUSING APPARATUS FOR SENSITIVE GAS SENSOR
    3.
    发明申请
    HOUSING APPARATUS FOR SENSITIVE GAS SENSOR 审中-公开

    公开(公告)号：US20200209148A1

    公开(公告)日：2020-07-02

    申请号：US16732511

    申请日：2020-01-02

    Applicant: International Business Machines Corporation

    Inventor： Yves Martin ,  William Green ,  Theodore G. van Kessel

    IPC: G01N21/17 ,  G01N21/39

    Abstract: A sensor housing apparatus includes a housing having an enclosure and outer assembly, at least one flow path extending through the housing, a gas sensor disposed in the enclosure and a thermal mass. The thermal mass is mounted within the enclosure in thermal communication with the gas sensor, and is configured to transfer thermal energy from the gas sensor to an ambient environment surrounding the housing and minimize temperature gradients adjacent the gas sensor.

    Solder-Pinning Metal Pads for Electronic Components
    4.
    发明申请
    Solder-Pinning Metal Pads for Electronic Components 审中-公开

    公开(公告)号：US20200100369A1

    公开(公告)日：2020-03-26

    申请号：US16140883

    申请日：2018-09-25

    Applicant: International Business Machines Corporation

    Inventor： Yves Martin ,  Tymon Barwicz

    IPC: H05K3/34 ,  H05K1/11 ,  H01L23/00 ,  G02B6/42 ,  G02B6/13

    Abstract: Solder-pinning metal pads for electronic components and techniques for use thereof to mitigate de-wetting are provided. In one aspect, a structure includes: a substrate; and a solder pad on the substrate, wherein the solder pad has sidewalls extending up from a surface thereof. For instance, the sidewalls can be present at edges of the solder pad, or inset from the edges of the solder pad. The sidewalls can be vertical or extend up from the solder pad at an angle. The sidewalls can be formed from the same material or a different material as the solder pad. A method is also provided that includes forming a solder pad on a substrate, the solder pad comprising sidewalls extending up from a surface thereof.

    OPTIMIZED STAND-OFFS AND MECHANICAL STOPS FOR PRECISE THREE DIMENSIONAL SELF-ALIGNMENT
    5.
    发明申请
    OPTIMIZED STAND-OFFS AND MECHANICAL STOPS FOR PRECISE THREE DIMENSIONAL SELF-ALIGNMENT 审中-公开

    公开(公告)号：US20190162902A1

    公开(公告)日：2019-05-30

    申请号：US15827306

    申请日：2017-11-30

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Tymon Barwicz ,  Yves Martin ,  Jae-Woong Nah

    IPC: G02B6/13 ,  G02B6/42

    CPC classification number: G02B6/13 ,  G02B6/423 ,  G02B6/4232 ,  G02B6/4238 ,  G02B6/4249

    Abstract: A method for assembling a semiconductor device includes: receiving a first chip including a plurality of first bonding pads, a first standoff and a second standoff, wherein a first solder is deposited on each of the first bonding pads; depositing a second solder on each of the first and second standoffs; arranging a second chip over the first chip, wherein the second chip includes a plurality of second bonding pads, and at least one of the second bonding pads has a corresponding first bonding pad; heating the second chip over a melting point of the second solder to melt the second solder, and placing the second chip on the first chip to touch and solidify the second solder on each of the first and second standoffs; performing a reflow process to melt the first solder on each of the first bonding pads so that at least one of the first solders touches a corresponding second bonding pad; and waiting a predetermined period of time to allow the second chip to move until a side edge of the second chip touches a waveguide of the first chip.

    Optimized solder pads for solder induced alignment of opto-electronic chips
    7.
    发明授权
    Optimized solder pads for solder induced alignment of opto-electronic chips 有权

    公开(公告)号：US09869831B2

    公开(公告)日：2018-01-16

    申请号：US15333847

    申请日：2016-10-25

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Tymon Barwicz ,  Yves Martin

    IPC: G02B6/42 ,  G02B6/12

    CPC classification number: G02B6/4232 ,  G02B6/12002 ,  G02B6/12004 ,  H01L2224/83192 ,  H01S5/0224 ,  H01S5/02268 ,  H01S5/02272 ,  H01S5/02469

    Abstract: A technique relates to assembling a multi-chip system. A first chip stack element having two major surfaces and a first solder pad, a first vertical stop, a first lateral stop and a first waveguiding element is provided. A second chip stack element having two major surfaces and including a second solder pad, a flow resistor connected to the second solder pad, a second vertical stop, a second lateral stop, a reservoir pad connected to the flow resistor, and a second waveguiding element is provided. A solder material is plated to form a plated solder pad. A technique includes pre-aligning the first chip stack element and the second chip stack element, raising the temperature to a temperature above the melting temperature of the solder material, and flowing solder through the flow resistor. Aspects include aligning the first and second waveguiding elements and cooling the connected assembly to re-solidify the solder material.

    Single edge coupling of chips with integrated waveguides
    10.
    发明授权
    Single edge coupling of chips with integrated waveguides 有权

    公开(公告)号：US10527787B1

    公开(公告)日：2020-01-07

    申请号：US16270886

    申请日：2019-02-08

    Applicant: International Business Machines Corporation

    Inventor： Yves Martin ,  Jason S. Orcutt ,  Tymon Barwicz ,  William Green

    IPC: G02B6/12 ,  G02B6/125 ,  G02B6/124 ,  G02B6/136

    Abstract: Techniques are provided for single edge coupling of chips with integrated waveguides. For example, a package structure includes a first chip with a first critical edge, and a second chip with a second critical edge. The first and second chips include integrated waveguides with end portions that terminate on the first and second critical edges. The second chip includes a signal reflection structure that is configured to reflect an optical signal propagating in one or more of the integrated waveguides of the second chip. The first and second chips are edge-coupled at the first and second critical edges such that the end portions of the integrated waveguides of the first and second chips are aligned to each other, and wherein all signal input/output between the first and second chips occurs at the single edge-coupled interface.

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