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21.发明授权公开(公告)号：US11763054B2
公开(公告)日：2023-09-19
申请号：US17384483
申请日：2021-07-23
Applicant: Imagination Technologies Limited
Inventor： Sam Elliott , Robert McKerney , Max Freiburghaus
IPC: G06F30/3323 , G06F119/16
CPC classification number: G06F30/3323 , G06F2119/16
Abstract: Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant kth difference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.
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公开(公告)号：US11645042B2
公开(公告)日：2023-05-09
申请号：US17547071
申请日：2021-12-09
Applicant: Imagination Technologies Limited
Inventor： Jonas Kallen , Sam Elliott
CPC classification number: G06F7/556 , G06F7/4873 , G06F7/727
Abstract: A binary logic circuit for determining the ratio x/d where x is a variable integer input, the binary logic circuit comprising: a logarithmic tree of modulo units each configured to calculate x[a:b]mod d for respective block positions a and b in x where b>a with the numbering of block positions increasing from the most significant bit of x up to the least significant bit of x, the modulo units being arranged such that a subset of M−1 modulo units of the logarithmic tree provide x[0:m]mod d for all m∈{1, M}, and, on the basis that any given modulo unit introduces a delay of 1: all of the modulo units are arranged in the logarithmic tree within a delay envelope of ┌log 2M┐; and more than M−2u of the subset of modulo units are arranged at the maximal delay of ┌log 2M┐, where 2u is the power of 2 immediately smaller than M.
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公开(公告)号：US20230097314A1
公开(公告)日：2023-03-30
申请号：US18076338
申请日：2022-12-06
Applicant: Imagination Technologies Limited
Inventor： Sam Elliott , Rachel Edmonds
IPC: G06F30/3323
Abstract: A hardware design for a component that evaluates a main algebraic expression comprising at least two variables is verified, the main algebraic expression being representable as a lossless combination of a plurality of sub-algebraic expressions, and one or more of the at least two variables can be constrained to cause an instantiation of the hardware design to evaluate each of the sub-algebraic expressions. An instantiation of the hardware design is verified as correctly evaluating each of the plurality of sub-algebraic expressions, and the instantiation of the hardware design is formally evaluated as correctly evaluating one or more combinations of sub-algebraic expressions, wherein the one or more combinations comprises a combination that is equivalent to the main algebraic expression.
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公开(公告)号：US20210350054A1
公开(公告)日：2021-11-11
申请号：US17384599
申请日：2021-07-23
Applicant: Imagination Technologies Limited
Inventor： Sam Elliott
IPC: G06F30/33 , G06F30/3323 , G06F30/337 , G01R31/3183
Abstract: A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) a plurality of leaf data transformation components which do not have children, and (ii) one or more parent data transformation components which each comprise one or more child data transformation components. For each of the plurality of leaf data transformation components, it is verified that an instantiation of the hardware design for the leaf data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. For each of the one or more parent data transformation components, it is formally verified, using a formal verification tool, that an instantiation of an abstracted hardware design for the parent data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. The abstracted hardware design for the parent data transformation component represents each of the one or more child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component is configured to produce a specific output transaction with a causal deterministic relationship to the specific input transaction.
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公开(公告)号：US20210157964A1
公开(公告)日：2021-05-27
申请号：US17167698
申请日：2021-02-04
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari , Sam Elliott
IPC: G06F30/3312
Abstract: Methods and systems for verifying that logic for implementing a pipelined process in hardware correctly moves data through the pipelined process. The method includes: (a) monitoring data input to the pipelined process to determine when watched data has been input to the pipelined process; (b) in response to determining the watched data has been input to the pipelined process counting a number of progressing clock cycles for the watched data; and (c) evaluating an assertion written in an assertion based language, the assertion establishing that when the watched data is output from the pipelined process the counted number of progressing clock cycles for the watched data should be equal to one of one or more predetermined values.
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Patent Agency Ranking
公开(公告)号：US10460058B2
公开(公告)日：2019-10-29
申请号：US16249834
申请日：2019-01-16
Applicant: Imagination Technologies Limited
Inventor： Sam Elliott
Abstract: A method of exhaustively verifying a property of a hardware design to implement a floating point power function. The method includes, formally verifying that the hardware design is recurrent over sets of β input exponents, wherein β is an integer that is a multiple of the reciprocal of the exponent of the power function; and for each recurrent input range of the hardware design, exhaustively simulating the hardware design over a simulation range to verify the property is true over the simulation range, wherein the simulation range comprises only β input exponents.
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27.发明申请公开(公告)号：US20190311075A1
公开(公告)日：2019-10-10
申请号：US16373774
申请日：2019-04-03
Applicant: Imagination Technologies Limited
Inventor： Sam Elliott
IPC: G06F17/50
Abstract: Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by formally verifying that the output of an instantiation of the hardware design produces the same output as an instantiation of a hardware design for another data transformation pipeline for a predetermined set of transactions under a constraint that substantially equivalent data transformation elements between the data transformation pipelines produce the same output(s) in response to the same input(s).
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公开(公告)号：US20170316116A1
公开(公告)日：2017-11-02
申请号：US15492205
申请日：2017-04-20
Applicant: Imagination Technologies Limited
Inventor： Sam Elliott
CPC classification number: G06F17/504 , G06F7/483 , G06F7/552 , G06F7/556 , G06F2217/12
Abstract: A method of exhaustively verifying a property of a hardware design to implement a floating point power function. The method includes, formally verifying that the hardware design is recurrent over sets of β input exponents, wherein β is an integer that is a multiple of the reciprocal of the exponent of the power function; and for each recurrent input range of the hardware design, exhaustively simulating the hardware design over a simulation range to verify the property is true over the simulation range, wherein the simulation range comprises only β input exponents.
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公开(公告)号：US20160321386A1
公开(公告)日：2016-11-03
申请号：US15143772
申请日：2016-05-02
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari , Sam Elliott
IPC: G06F17/50
CPC classification number: G06F17/5031 , G06F17/5022 , G06F2217/84
Abstract: Methods and systems for verifying that logic for implementing a pipelined process in hardware correctly moves data through the pipelined process. The method includes: (a) monitoring data input to the pipelined process to determine when watched data has been input to the pipelined process; (b) in response to determining the watched data has been input to the pipelined process counting a number of progressing clock cycles for the watched data; and (c) evaluating an assertion written in an assertion based language, the assertion establishing that when the watched data is output from the pipelined process the counted number of progressing clock cycles for the watched data should be equal to one of one or more predetermined values.
Abstract translation: 用于验证用于在硬件中实现流水线过程的逻辑的方法和系统通过流水线过程正确地移动数据。 该方法包括：（a）监视输入到流水线过程的数据，以确定观看数据何时已被输入流水线过程; （b）响应于确定所观看的数据已被输入到流水线处理中，对所观看的数据计数多个进行时钟周期; 以及（c）评估以基于断言的语言书写的断言，该断言确定当从流水线处理输出观看数据时，所观察数据的计数的进行时钟周期数应当等于一个或多个预定值 。
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公开(公告)号：US20240037303A1
公开(公告)日：2024-02-01
申请号：US18377746
申请日：2023-10-06
Applicant: Imagination Technologies Limited
Inventor： Simon Gaulter , Thomas Ferrere , Faizan Nazar , Sam Elliott
IPC: G06F30/33
CPC classification number: G06F30/33
Abstract: Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.
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