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公开(公告)号：US10706591B2
公开(公告)日：2020-07-07
申请号：US16142866
申请日：2018-09-26
Applicant: Intel Corporation
Inventor： Karthik Vaidyanathan , Prasoonkumar Surti , Hugues Labbe , Atsuo Kuwahara , Sameer Kp , Jonathan Kennedy , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh
Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
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公开(公告)号：US10672175B2
公开(公告)日：2020-06-02
申请号：US15489177
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Devan Burke , Adam T. Lake , Jeffery S. Boles , John H. Feit , Karthik Vaidyanathan , Abhishek R. Appu , Joydeep Ray , Subramaniam Maiyuran , Altug Koker , Balaji Vembu , Murali Ramadoss , Prasoonkumar Surti , Eric J. Hoekstra , Gabor Liktor , Jonathan Kennedy , Slawomir Grajewski , Elmoustapha Ould-Ahmed-Vall
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.
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公开(公告)号：US20190087188A1
公开(公告)日：2019-03-21
申请号：US15709213
申请日：2017-09-19
Applicant: Intel Corporation
Inventor： Karthik Vaidyanathan , Tomasz Janczak , Travis Schluessler , Subramaniam Maiyuran
CPC classification number: G06F9/30123 , G06F9/3009 , G06F9/485 , G06F9/4881 , G06F9/505 , G06T15/005
Abstract: An apparatus to facilitate register allocation is disclosed. The apparatus includes an execution unit (EU) to execute processing threads. The EU includes a plurality of registers and register allocation logic to map the plurality of registers into logical register banks and allocate the processing threads to one or more of the logical register banks.
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24.发明申请公开(公告)号：US20180308277A1
公开(公告)日：2018-10-25
申请号：US15494778
申请日：2017-04-24
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Karthik Vaidyanathan , Atsuo Kuwahara , Hugues Labbe , Sameer Kp , Jonathan Kennedy , Abhishek R. Appu , Jeffery S. Boles , Balaji Vembu , Michael Apodaca , Slawomir Grajewski , Gabor Liktor , David M. Cimini , Andrew T. Lauritzen , Travis T. Schluessler , Murali Ramadoss , Abhishek Venkatesh , Joydeep Ray , Kai Xiao , Ankur N. Shah , Altug Koker
CPC classification number: G06T15/405 , G06T1/20 , G06T11/40 , G06T15/005 , G06T15/30 , G06T15/40 , G06T17/20 , G06T2210/52
Abstract: The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles surface triangles in one or more exclusion zones.
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公开(公告)号：US10109078B1
公开(公告)日：2018-10-23
申请号：US15483701
申请日：2017-04-10
Applicant: Intel Corporation
Inventor： Karthik Vaidyanathan , Prasoonkumar Surti , Hugues Labbe , Atsuo Kuwahara , Sameer Kp , Jonathan Kennedy , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh
Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
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Patent Agency Ranking
公开(公告)号：US20180286115A1
公开(公告)日：2018-10-04
申请号：US15477016
申请日：2017-04-01
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Karthik Vaidyanathan , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh , Devan Burke , Philip R. Laws , Subramaniam Maiyuran , Abhishek R. Appu , ElMoustapha Ould-Ahmed-Vall , Peter L. Doyle
CPC classification number: G06T15/80 , G06F9/50 , G06F9/5011 , G06T1/20 , G06T5/20
Abstract: An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel regrouper communicatively coupled to the conditional pixel shader to regroup pixels based on whether the one or more pixels are determined to meet the shader condition. Another embodiment of a conditional shader apparatus may include a thread analyzer to determine if a set of threads meet a thread condition, and a conditional kernel loader communicatively coupled to the thread analyzer to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition. Other embodiments are disclosed and claimed.
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公开(公告)号：US09672657B2
公开(公告)日：2017-06-06
申请号：US15261893
申请日：2016-09-10
Applicant: Intel Corporation
Inventor： Carl J. Munkberg , Karthik Vaidyanathan , Jon N. Hasselgren , Franz P. Clarberg , Tomas G. Akenine-Moller , Marco Salvi
CPC classification number: G06T15/503 , G06T5/50 , G06T15/06 , G06T15/50 , G06T15/506 , G06T2200/21 , G06T2207/10052 , H04N5/23229
Abstract: Real-time light field reconstruction for defocus blur may be used to handle the case of simultaneous defocus and motion blur. By carefully introducing a few approximations, a very efficient sheared reconstruction filter is derived, which produces high quality images even for a very low number of input samples in some embodiments. The algorithm may be temporally robust, and is about two orders of magnitude faster than previous work, making it suitable for both real-time rendering and as a post-processing pass for high quality rendering in some embodiments.
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公开(公告)号：US09569883B2
公开(公告)日：2017-02-14
申请号：US14103951
申请日：2013-12-12
Applicant: Intel Corporation
Inventor： Karthik Vaidyanathan , Marco Salvi , Robert M. Toth
CPC classification number: G06T15/503 , G06T1/20 , G06T2200/12
Abstract: In some embodiments, a given frame or picture may have different shading rates. In one embodiment in some areas of the frame or picture the shading rate may be less than once per pixel and in other places it may be once per pixel. Examples where the shading rate may be reduced include areas where there is motion and camera defocus, areas of peripheral blur, and in general, any case where the visibility is reduced anyway. The shading rate may be changed in a region, such as a shading quad, by changing the size of the region.
Abstract translation: 在一些实施例中，给定的帧或图片可以具有不同的着色速率。 在一个实施例中，在帧或图像的某些区域中，阴影率可以小于每像素一次，而在其它位置，每个像素可以是一次。 可以减少阴影率的示例包括存在运动和照相机散焦的区域，外围模糊的区域，以及一般来说，任何可见度被降低的情况。 通过改变区域的大小，可以在诸如阴影四边形的区域中改变阴影率。
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公开(公告)号：US12198221B2
公开(公告)日：2025-01-14
申请号：US18436494
申请日：2024-02-08
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Narayan Srinivasa , Feng Chen , Joydeep Ray , Ben J. Ashbaugh , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Balaji Vembu , Tsung-Han Lin , Kamal Sinha , Rajkishore Barik , Sara S. Baghsorkhi , Justin E. Gottschlich , Altug Koker , Nadathur Rajagopalan Satish , Farshad Akhbari , Dukhwan Kim , Wenyin Fu , Travis T. Schluessler , Josh B. Mastronarde , Linda L Hurd , John H. Feit , Jeffery S. Boles , Adam T. Lake , Karthik Vaidyanathan , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu
Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.
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公开(公告)号：US20240394956A1
公开(公告)日：2024-11-28
申请号：US18675746
申请日：2024-05-28
Applicant: Intel Corporation
Inventor： Sven Woop , Michael J. Doyle , Sreenivas Kothandaraman , Karthik Vaidyanathan , Abhishek R. Appu , Carsten Benthin , Prasoonkumar Surti , Holger Gruen , Stephen Junkins , Adam Lake , Bret G. Alfieri , Gabor Liktor , Joshua Barczak , Won-Jong Lee
Abstract: Apparatus and method for efficient graphics processing including ray tracing. For example, one embodiment of a graphics processor comprises: execution hardware logic to execute graphics commands and render images; an interface to couple functional units of the execution hardware logic to a tiled resource; and a tiled resource manager to manage access by the functional units to the tiled resource, a functional unit of the execution hardware logic to generate a request with a hash identifier (ID) to request access to a portion of the tiled resource, wherein the tiled resource manager is to determine whether a portion of the tiled resource identified by the hash ID exists, and if not, to allocate a new portion of the tiled resource and associate the new portion with the hash ID.
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