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公开(公告)号：US11657472B2
公开(公告)日：2023-05-23
申请号：US17707118
申请日：2022-03-29
申请人： INTEL CORPORATION
发明人： Carsten Benthin , Sven Woop , Ingo Wald
CPC分类号： G06T1/20 , G06F9/3877 , G06T15/005 , G06T15/06 , G06T17/10 , G06T2210/12
摘要： Apparatus and method for compressing an acceleration data structure such as a bounding volume hierarchy (BVH). For example, one embodiment of a graphics processing apparatus comprises: one or more cores to execute graphics instructions including instructions to perform ray tracing operations; and compression circuitry to compress lowest level nodes of a hierarchical acceleration data structure comprising a plurality of hierarchically arranged nodes, each of the lowest level nodes comprising pointers to leaf data; the compression circuitry to quantize the lowest level nodes to generate quantized lowest level nodes and to store each quantized lowest level node and associated leaf data without the pointers to the leaf data.
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公开(公告)号：US11263800B2
公开(公告)日：2022-03-01
申请号：US16728375
申请日：2019-12-27
申请人： Intel Corporation
摘要： Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.
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公开(公告)号：US11189076B2
公开(公告)日：2021-11-30
申请号：US16929671
申请日：2020-07-15
申请人： INTEL CORPORATION
发明人： Karthik Vaidyanathan , Sven Woop , Carsten Benthin
摘要： Apparatus and method for preventing re-traversal of a prior path on a restart. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a graphics scene; a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes, wherein the BVH comprises a specified number of child nodes at a current BVH level beneath a parent node in the hierarchy; circuitry to traverse one or more of the rays through the BVH to form a current traversal path and intersect the one or more rays with primitives contained within the nodes, wherein the circuitry is to process entries from the top of a first data structure comprising entries each associated with a child node at the current BVH level, the entries being ordered from top to bottom based on a sorted distance of each respective child node.
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公开(公告)号：US10957095B2
公开(公告)日：2021-03-23
申请号：US16056222
申请日：2018-08-06
申请人： Intel Corporation
发明人： Karthik Vaidyanathan , Won-Jong Lee , Gabor Liktor , John G. Gierach , Pawel Majewski , Prasoonkumar Surti , Carsten Benthin , Sven Woop , Thomas Raoux
摘要： Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.
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公开(公告)号：US10600231B2
公开(公告)日：2020-03-24
申请号：US15924112
申请日：2018-03-16
申请人： Intel Corporation
摘要： Embodiments provide for a graphics processing apparatus including a graphics processing unit having bounding volume logic to operate on a compressed bounding volume hierarchy, wherein each bounding volume node stores a parent bounding volume and multiple child bounding volumes that are encoded relative to the parent bounding volume.
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公开(公告)号：US11900498B2
公开(公告)日：2024-02-13
申请号：US16823741
申请日：2020-03-19
申请人： Intel Corporation
发明人： Saikat Mandal , Prasoonkumar Surti , Sven Woop
IPC分类号： G06T1/60 , G06T1/20 , G06T15/00 , G06T17/10 , G06F9/38 , G06F7/24 , G06F7/02 , G06F7/505 , G06T15/08
CPC分类号： G06T1/20 , G06F7/02 , G06F7/24 , G06F7/505 , G06F9/3885 , G06T15/005 , G06T15/08 , G06T17/10
摘要： Apparatus and method for stable and short latency sorting. For example, one embodiment of a processor comprises: an input circuit to receive a set of N input values to be sorted into a sorted order; comparison circuitry to compare each input value with all other input values in parallel to generate at least N*(N−1)/2 comparison result values; matrix generation circuitry and/or logic to generate a result matrix having a row associated with each input value, a plurality of bits in each row comprising comparison result values indicating results of comparisons with other input values, wherein a first region of the result matrix is to store a first set of bits comprising the N*(N−1)/2 comparison result values and a second region of the result matrix, opposite the first region, is to store a second set of bits comprising an inverse of the N*(N−1)/2 comparison result values; a parallel adder circuit to perform parallel additions of the bits in each row to generate N unique result values; and sorting circuitry to index into the N unique result values to return the sorted order.
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公开(公告)号：US11776196B2
公开(公告)日：2023-10-03
申请号：US17868610
申请日：2022-07-19
申请人： INTEL CORPORATION
发明人： Sven Woop , Attila Afra , Carsten Benthin , Ingo Wald , Johannes Guenther
CPC分类号： G06T15/005 , G06T1/20 , G06T15/06 , G06T17/00 , G09G2360/00
摘要： A graphics processing apparatus comprising bounding volume hierarchy (BVH) construction circuitry to perform a spatial analysis and temporal analysis related to a plurality of input primitives and responsively generate a BVH comprising spatial, temporal, and spatial-temporal components that are hierarchically arranged, wherein the spatial components include a plurality of spatial nodes with children, the spatial nodes bounding the children using spatial bounds, and the temporal components comprise temporal nodes with children, the temporal nodes bounding their children using temporal bounds and the spatial-temporal components comprise spatial-temporal nodes with children, the spatial-temporal nodes bounding their children using spatial and temporal bounds; and ray traversal/intersection circuitry to traverse a ray or a set of rays through the BVH in accordance with the spatial and temporal components.
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公开(公告)号：US11189074B2
公开(公告)日：2021-11-30
申请号：US16890254
申请日：2020-06-02
申请人： INTEL CORPORATION
发明人： Carsten Benthin , Sven Woop
摘要： An apparatus and method for efficiently reconstructing a BVH. For example, one embodiment of a method comprises: constructing an object bounding volume hierarchy (BVH) for each object in a scene, each object BVH including a root node and one or more child nodes based on primitives included in each object; constructing a top-level BVH using the root nodes of the individual object BVHs; performing an analysis of the top-level BVH to determine whether the top-level BVH comprises a sufficiently efficient arrangement of nodes within its hierarchy; and reconstructing at least a portion of the top-level BVH if a more efficient arrangement of nodes exists, wherein reconstructing comprises rebuilding the portion of the top-level BVH until one or more stopping criteria have been met, the stopping criteria defined to prevent an entire rebuilding of the top-level BVH.
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公开(公告)号：US11069118B2
公开(公告)日：2021-07-20
申请号：US16749856
申请日：2020-01-22
申请人： INTEL CORPORATION
发明人： Sven Woop , Attila Afra , Carsten Benthin , Ingo Wald , Johannes Guenther
摘要： A graphics processing apparatus comprising bounding volume hierarchy (BVH) construction circuitry to perform a spatial analysis and temporal analysis related to a plurality of input primitives and responsively generate a BVH comprising spatial, temporal, and spatial-temporal components that are hierarchically arranged, wherein the spatial components include a plurality of spatial nodes with children, the spatial nodes bounding the children using spatial bounds, and the temporal components comprise temporal nodes with children, the temporal nodes bounding their children using temporal bounds and the spatial-temporal components comprise spatial-temporal nodes with children, the spatial-temporal nodes bounding their children using spatial and temporal bounds; and ray traversal/intersection circuitry to traverse a ray or a set of rays through the BVH in accordance with the spatial and temporal components.
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公开(公告)号：US20210097750A1
公开(公告)日：2021-04-01
申请号：US16585880
申请日：2019-09-27
申请人： Intel Corporation
发明人： Sven Woop , Prasoonkumar Surti , Karthik Vaidyanathan , Carsten Benthin , Joshua Barczak , Saikat Mandal
摘要： An apparatus and method for merging primitives and coordinating between vertex and ray transformations on a shared transformation unit. For example, one embodiment of a graphics processor comprises: a queue comprising a plurality of entries; ordering circuitry/logic to order triangles front to back within the queue; pairing circuitry/logic to identify triangles in the queue sharing an edge and to merge the triangles sharing an edge to produce merged triangle pairs; and shared transformation circuitry to alternate between performing vertex transformations on vertices of the merged triangle pairs and to performing ray transformations on ray direction/origin data.
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