公开(公告)号：US20220077856A1

公开(公告)日：2022-03-10

申请号：US17525894

申请日：2021-11-13

Applicant: Intel Corporation

Inventor： Yi Peng ,  Brandon Gordon ,  Mahesh A. Iyer ,  Krishna Nagar

IPC: H03K19/177 ,  G06F30/343

Abstract: An integrated circuit includes a monitored circuit and a signal analyzer circuit. The signal analyzer circuit includes a logic circuit that determines if a condition signal satisfies a condition to generate an output signal. A first-in-first-out (FIFO) buffer circuit stores opportunistic data indicated by a monitored signal received from the monitored circuit in response to the output signal indicating if the condition signal satisfies the condition. A communication channel transmits the opportunistic data stored in the FIFO buffer circuit outside the integrated circuit.

公开(公告)号：US20210384912A1

公开(公告)日：2021-12-09

申请号：US17407700

申请日：2021-08-20

Applicant: Intel Corporation

Inventor： Scott Jeremy Weber ,  Aravind Raghavendra Dasu ,  Mahesh A. Iyer ,  Patrick Koeberl

IPC: H03K19/17756 ,  H01L25/065 ,  H01L25/00

Abstract: An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces as well as compute elements that may also be application-specific. The memory in the base die may be directly accessed by the programmable fabric die using a low-latency, high capacity, and high bandwidth interface.

公开(公告)号：US10169518B1

公开(公告)日：2019-01-01

申请号：US15342286

申请日：2016-11-03

Applicant: Intel Corporation

Inventor： Mahesh A. Iyer

IPC: G06F17/50

Abstract: An integrated circuit design may include registers and combinational logic. The registers may be reset using an original reset sequence. Integrated circuit design computing equipment may perform register moves within the circuit design, whereby registers are moved across one or more portions of the combinational logic. When moving the registers, counter values may be maintained for a group of non-justifiable elements within the combinational logic, across which the registers may move. The counter values may be maintained and updated on a per element, per clock domain basis to account for register moves across the corresponding non-justifiable elements. The maximum counter value for each clock domain may be chosen as an adjustment value that may be used to generate an adjustment sequence. The adjustment sequence may be prepended to the original reset sequence to generate an adjusted reset sequence that properly resets registers within the integrated circuit after registers moves.

公开(公告)号：US10157247B2

公开(公告)日：2018-12-18

申请号：US15718424

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Mahesh A. Iyer ,  Vasudeva M. Kamath

IPC: G06F17/50

Abstract: A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. The retimed design is verified to determine whether it is structurally correct by performing a plurality of iterations of register retiming on the retimed design, wherein each iteration accounts for the retiming of registers in the system driven by a different clock.

公开(公告)号：US20180349544A1

公开(公告)日：2018-12-06

申请号：US15610223

申请日：2017-05-31

Applicant: Intel Corporation

Inventor： Mahesh A. Iyer ,  Ian Milton ,  Dai Le

IPC: G06F17/50

Abstract: An integrated circuit design may include registers and combinational logic. Integrated circuit design computing equipment may perform retiming for the circuit design, where registers are moved across one or more portions of the combinational logic. The registers may be retimed while considering hybrid initial states of the registers. At least some of the registers may have don't-care initial states. When performing backward retiming, initial states of the retimed registers may be computed that is consistent with the original initial state and functionality of the combinational logic while maximizing the number of don't-care initial states. When performing forward retiming across non-justifiable combinational elements, any don't-care initial states may be assumed to be equal to a deterministic binary value, and the initial states of the retimed registers may be computed that is consistent with the original initial states and functionality of the combinational logic.

公开(公告)号：US20180018417A1

公开(公告)日：2018-01-18

申请号：US15718424

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Mahesh A. Iyer ,  Vasudeva M. Kamath

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5054 ,  G06F17/5081 ,  G06F2217/84

Abstract: A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. The retimed design is verified to determine whether it is structurally correct by performing a plurality of iterations of register retiming on the retimed design, wherein each iteration accounts for the retiming of registers in the system driven by a different clock.

公开(公告)号：US12216150B2

公开(公告)日：2025-02-04

申请号：US18086616

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Dheeraj Subbareddy ,  Ankireddy Nalamalpu ,  Mahesh A. Iyer ,  Dhananjay Raghavan

IPC: G01R31/26 ,  G01R31/28 ,  G01R31/30 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/3193

Abstract: A method includes mapping an aging measurement circuit (AMC) into the core fabric of an FPGA and operating the AMC for a select time period. During the select period of time, the AMC counts transition of a signal propagating through the AMC. Timing information based on the counted transitions is stored in a timing model in a memory. The timing information represents an aging characteristic of the core fabric at a time that the AMC is operated. An EDA toolchain uses the timing information in the timing model to generate a timing guard-band for the configurable IC die. The AMC is removed from the core fabric and another circuit device is mapped and fitted into the core fabric using the generated timing guard-band models. The circuit device is operated in the configurable IC die based on the timing guard-band models.

公开(公告)号：US11609262B2

公开(公告)日：2023-03-21

申请号：US16232023

申请日：2018-12-25

Applicant: Intel Corporation

Inventor： Dheeraj Subbareddy ,  Ankireddy Nalamalpu ,  Mahesh A. Iyer ,  Dhananjay Raghavan

IPC: G01R31/26 ,  G01R31/317 ,  G01R31/3193 ,  G01R31/28 ,  G01R31/30 ,  G01R31/3185

Abstract: An integrated circuit die includes a core fabric configurable to include an aging measurement circuit and a device manager coupled to the core fabric to operate the aging measurement circuit for a select period of time. The aging measurement circuit includes a counter to count transitions of a signal propagating through the aging measurement circuit during the select period of time when the aging measurement circuit is operating. The transitions of the signal counted by the counter during the select period of time are a measure of an aging characteristic of the integrated circuit die.

公开(公告)号：US20230018414A1

公开(公告)日：2023-01-19

申请号：US17956565

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Martin Langhammer ,  Gregg William Baeckler ,  Sergey Vladimirovich Gribok ,  Mahesh A. Iyer

IPC: G06F1/08 ,  H03K19/17736

Abstract: The present disclosure describes techniques for incorporating pipelined DSP blocks or other types of embedded functions into a logic circuit with a slower clock rate without any clock crossing complexities, and at the same time managing the power consumption of the more complex design that results from it. The techniques include generating a faster clock or several faster clocks that may have a faster clock rate than the clock used by the logic circuit and that may be used as clock input to the embedded pipelined DSP blocks. In addition, the present disclosure describes techniques for generating, improving, and using the faster clock to sample the output of a logic circuit using pulses of generated faster clock, which may allow to increase the clock frequency of the circuit to an optimal level, while maintaining functional correctness.

公开(公告)号：US11368158B2

公开(公告)日：2022-06-21

申请号：US16019297

申请日：2018-06-26

Applicant: Intel Corporation

Inventor： Dheeraj Subbareddy ,  Ankireddy Nalamalpu ,  Mahesh A. Iyer

IPC: H03K19/17764 ,  H03K19/17724 ,  H03K19/17736 ,  G06F30/30 ,  G06F30/39 ,  G06F117/06

Abstract: A method of handling integrated circuit dies with defects is provided. After forming a plurality of dies on one or more silicon wafers, test equipment may be used to identify defects on the dies and to create corresponding defect maps. The defect maps can be combined to form an aggregate defect map. Circuit design tools may create keep-out zones from the aggregate defect map and run learning experiments on each die, while respecting the keep-out zones, to compute design metrics. The circuit design tools may further create larger keep-out zones and run additional learning experiments on each die while respecting the larger keep-out zones to compute additional design metrics. The dies can be binned into different Stock Keeping Units (SKUs) based on one or more of the computed design metrics. Circuit design tools automatically respect the keep-out regions for these dies to program them correctly in the field.