公开(公告)号：US10762006B2

公开(公告)日：2020-09-01

申请号：US15476901

申请日：2017-03-31

申请人： INTEL CORPORATION

发明人： Jeffrey A. Pihlman ,  Ramamurthy Krithivas

IPC分类号： G06F13/16 ,  G06F9/44 ,  G06F9/4401

摘要： Various embodiments are generally directed to an apparatus, method and other techniques to determine one or more memory channels of a plurality of memory channels to be enabled based on an indication received from a basic input/output system (BIOS), determine whether a number of the one or more memory channels to be enabled is greater than a maximum number of memory channels permitted, cause a platform reset if the number of the one or more memory channels is greater than the maximum number of memory channels, and permit enablement of the one or more memory channels if the number of the one or more memory channels is not greater than the maximum number of memory channels.

公开(公告)号：US10509435B2

公开(公告)日：2019-12-17

申请号：US15279535

申请日：2016-09-29

申请人： Intel Corporation

发明人： Ramamurthy Krithivas ,  Mark A. Bordogna ,  James M. Sepko

IPC分类号： G06F1/14 ,  G06F1/12 ,  G06F21/72 ,  G06F11/34

摘要： Disclosed herein are systems and methods for initializing and synchronizing a protected real time clock via hardware connections. For example, in some embodiments, a protected real time clock on a trusted execution environment may initialize via a hardware connection to a master clock, which is synchronized to a trusted time source via a hardware connection. In some embodiments, a protected real time clock on a trusted execution environment may initialize to a master clock during a system hardware reset sequence. In some embodiments, before a system is running normally, a real time clock on an integrated Intellectual Property agent may initialize and synchronize to a protected real time clock via a hardware connection. In some embodiments, after a system is running normally, a real time clock on a discrete device may initialize and synchronize to a protected real time clock via a hardware connection.

公开(公告)号：US10116518B2

公开(公告)日：2018-10-30

申请号：US15599087

申请日：2017-05-18

申请人： Intel Corporation

发明人： Ramamurthy Krithivas ,  Narayan Ranganathan ,  Mohan J. Kumar ,  John C. Leung

IPC分类号： H04L12/24 ,  H04L12/855 ,  H04L29/12

摘要： Mechanisms to enable management controllers to learn the control plane hierarchy in data center environments. The data center is configured in a physical hierarchy including multiple pods, racks, trays, and sleds and associated switches. Management controllers at various levels in a control plane hierarchy and associated with switches in the physical hierarchy are configured to add their IP addresses to DHCP (Dynamic Host Control Protocol) responses that are generated by a DCHP server in response to DCHP requests for IP address requests initiated by DHCP clients including manageability controllers, compute nodes and storage nodes in the data center. As the DCHP response traverses each of multiple switches along a forwarding path from the DCHP server to the DHCP client, an IP address of the manageability controller associated with the switch is inserted. Upon receipt at the DHCP client, the inserted IP addresses are extracted and used to automate learning of the control plane hierarchy.

公开(公告)号：US10048744B2

公开(公告)日：2018-08-14

申请号：US14554384

申请日：2014-11-26

申请人： Intel Corporation

发明人： Tessil Thomas ,  Phani Kumar Kandula ,  Ramamurthy Krithivas ,  Howard Chin ,  Ian M. Steiner ,  Vivek Garg

IPC分类号： G06F1/32 ,  G06F1/20

摘要： In an embodiment, a processor includes a first chip of a multi-chip package (MCP). The first chip includes at least one core and first chip temperature control (TC) logic to assert a first power adjustment signal at a second chip of the MCP responsive to an indication that a first chip temperature of the first chip exceeds a first threshold. The processor also includes a conduit that includes a bi-directional pin to couple the first chip to the second chip within the MCP. The conduit is to transport the first power adjustment signal from the first chip to the second chip and the first power adjustment signal is to cause an adjustment of a second chip power consumption of the second chip. Other embodiments are described and claimed.

公开(公告)号：US09996711B2

公开(公告)日：2018-06-12

申请号：US14927973

申请日：2015-10-30

申请人： Intel Corporation

发明人： Ramamurthy Krithivas ,  Donald C. Soltis, Jr. ,  Bradley Burres

IPC分类号： G06F21/72 ,  G06F21/88 ,  G06F21/44 ,  G06F21/74 ,  G06F9/445

CPC分类号： G06F21/88 ,  G06F8/60 ,  G06F21/44 ,  G06F21/72 ,  G06F21/74

摘要： An integrated circuit (IC) provisioned for asset protection has a primary circuit portion, such as a microprocessor or system-on-chip, that can be selectively disabled and enabled via an operability control input. The IC includes a secure register to store lock state indicia and unlock criteria, where a signal at the operability control input is responsive to the lock state indicia. In operation, a firmware data store receives and stores firmware code that includes a lock/unlock command, and firmware data that includes an unlock key. An authorization module verifies authenticity of the firmware code. A lock/unlock (LUL) module is operative to write lock state indicia to the secure register based on the lock/unlock command only in response to a positive verification of the authenticity of the firmware code by the authorization module, and to write lock state indicia to the secure register.

公开(公告)号：US09569267B2

公开(公告)日：2017-02-14

申请号：US14659523

申请日：2015-03-16

申请人： Intel Corporation

发明人： Ramamurthy Krithivas ,  Balaji Parthasarathy

IPC分类号： G06F3/00 ,  G06F13/00 ,  G06F9/50 ,  G06F9/445 ,  G06F9/44 ,  G06F13/12

CPC分类号： G06F9/5011 ,  G06F1/26 ,  G06F9/4411 ,  G06F9/4418 ,  G06F9/44505 ,  G06F9/5072 ,  G06F9/5077 ,  G06F9/546 ,  G06F13/126

摘要： The present disclosure is directed to hardware-based inter-device resource sharing. For example, a remote orchestrator (RO) may provide instructions to cause a device to make at least one hardware resource available to other devices. An RO module in the device may interact with the RO and may configure a configuration module in the device based on instructions received from the RO. The configuration module may set a device configuration when the device transitions from a power off state to a power on state. The device may also comprise a processing module to process data based on the device configuration, interface technology (IT) and at least one hardware resource. The interface technology may allow the processing module and the at least one hardware resource to interact. The RO module may configure the IT to allow the at least one hardware resource to operate locally or remotely based on the instructions.

摘要翻译： 本公开涉及基于硬件的设备间资源共享。 例如，远程协调器（RO）可以提供指令以使设备使至少一个硬件资源可用于其他设备。 设备中的RO模块可以与RO交互，并且可以基于从RO接收到的指令在设备中配置配置模块。 当设备从电源关闭状态转换到电源接通状态时，配置模块可以设置设备配置。 该设备还可以包括用于基于设备配置，接口技术（IT）和至少一个硬件资源来处理数据的处理模块。 接口技术可以允许处理模块和至少一个硬件资源进行交互。 RO模块可以将IT配置为允许至少一个硬件资源基于指令在本地或远程操作。

公开(公告)号：US09535606B2

公开(公告)日：2017-01-03

申请号：US14580008

申请日：2014-12-22

申请人： Intel Corporation

发明人： Ramamurthy Krithivas ,  Eswaramoorthi Nallusamy ,  Mark A. Schmisseur

IPC分类号： G06F3/06 ,  G06F12/06

CPC分类号： G06F12/0692 ,  G06F9/45541 ,  G06F9/5077 ,  G06F2212/1041 ,  G06F2212/657

摘要： Apparatus, systems, and methods to implement a virtual serial presence detect operation for pooled memory are described. In one embodiment, a controller comprises logic to receive a request to establish a composed computing device, define a plurality of virtual memory devices to be associated with a composed computing device, allocate memory from a shared pool of physical memory to the plurality of virtual memory devices, create a plurality of virtual serial detects (vSPDs) for the plurality of virtual memory devices, and store the plurality of vSPDs in a linked list in an operational memory device. Other embodiments are also disclosed and claimed.

摘要翻译： 描述了用于实现池存储器的虚拟串行存在检测操作的装置，系统和方法。 在一个实施例中，控制器包括接收建立组合计算设备的请求的逻辑，定义要与组合计算设备相关联的多个虚拟存储器设备，将存储器从物理存储器的共享池分配给多个虚拟存储器 设备，为多个虚拟存储设备创建多个虚拟串行检测（vSPD），并将多个vSPD存储在操作存储器设备中的链表中。 还公开并要求保护其他实施例。

公开(公告)号：US20160179411A1

公开(公告)日：2016-06-23

申请号：US14581851

申请日：2014-12-23

申请人： Intel Corporation

发明人： Patrick Connor ,  Scott P. Dubal ,  Ramamurthy Krithivas ,  Chris Pavlas

IPC分类号： G06F3/06 ,  G06F11/20

CPC分类号： G06F3/0619 ,  G06F3/0629 ,  G06F3/0689 ,  G06F11/1076 ,  G06F11/2028 ,  G06F11/2038 ,  G06F11/2046 ,  G06F11/2094 ,  G06F2201/805

摘要： Examples may include techniques to provide redundant array of independent disks (RAID) services using a shared pool of configurable computing resources. Information for a data service being provided using the shared pool of configurable computing resources may be received. Logical servers hosting logical volume managers (LVMs) may be composed from at least a portion of the shared pool of configurable computing resources. In some examples, the hosted LVMs are capable of each providing a RAID service based, at least in part, on the received information for the data service.

摘要翻译： 示例可以包括使用可配置计算资源的共享池来提供独立磁盘（RAID）服务的冗余阵列的技术。 可以接收使用可配置计算资源的共享池提供的数据服务的信息。 托管逻辑卷管理器（LVM）的逻辑服务器可以由可配置计算资源的共享池的至少一部分组成。 在一些示例中，托管的LVM能够至少部分地基于所接收的用于数据服务的信息来提供RAID服务。