公开(公告)号：US20170290158A1

公开(公告)日：2017-10-05

申请号：US15085080

申请日：2016-03-30

申请人： Intel Corporation

发明人： Jeffrey A. Pihlman ,  John C. Tomlin

IPC分类号： H05K1/18 ,  H05K1/11 ,  H01L23/498 ,  H05K3/40 ,  H05K3/10 ,  H05K3/34 ,  H05K1/02 ,  H05K1/14

CPC分类号： H05K1/181 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/50 ,  H01R12/727 ,  H05K1/0262 ,  H05K1/0296 ,  H05K1/111 ,  H05K1/113 ,  H05K1/14 ,  H05K1/141 ,  H05K1/144 ,  H05K3/10 ,  H05K3/341 ,  H05K3/4007 ,  H05K2201/041 ,  H05K2201/042 ,  H05K2201/045 ,  H05K2201/10037 ,  H05K2201/10734 ,  H05K2201/2036

摘要： IC device assemblies including a power delivery bus board that is mounted to a primary PCB (i.e., motherboard) that further hosts a power-sink device and a power-source device. The bus board, as a secondary PCB, may be surface-mounted on a back side of the primary PCB opposite the power source and sink devices, which are mounted on the front side of the primary PCB. The bus board need only be dimensioned so as to bridge a length between first and second back-side regions of the primary PCB that are further coupled to a portion of the front-side pads employed by the power-sink device. The secondary PCB may be purpose-built for conveying power between the source and sink devices, and include, for example, short, wide traces, that may be formed from multiple heavyweight metallization layers.

公开(公告)号：US10762006B2

公开(公告)日：2020-09-01

申请号：US15476901

申请日：2017-03-31

申请人： INTEL CORPORATION

发明人： Jeffrey A. Pihlman ,  Ramamurthy Krithivas

IPC分类号： G06F13/16 ,  G06F9/44 ,  G06F9/4401

摘要： Various embodiments are generally directed to an apparatus, method and other techniques to determine one or more memory channels of a plurality of memory channels to be enabled based on an indication received from a basic input/output system (BIOS), determine whether a number of the one or more memory channels to be enabled is greater than a maximum number of memory channels permitted, cause a platform reset if the number of the one or more memory channels is greater than the maximum number of memory channels, and permit enablement of the one or more memory channels if the number of the one or more memory channels is not greater than the maximum number of memory channels.

公开(公告)号：US10123419B2

公开(公告)日：2018-11-06

申请号：US15085080

申请日：2016-03-30

申请人： Intel Corporation

发明人： Jeffrey A. Pihlman ,  John C. Tomlin

IPC分类号： H05K7/12 ,  H05K1/14 ,  H05K1/11 ,  H05K1/18 ,  H05K1/02 ,  H05K3/40 ,  H05K3/10 ,  H05K3/34 ,  H01L23/498 ,  H01R12/72

摘要： IC device assemblies including a power delivery bus board that is mounted to a primary PCB (i.e., motherboard) that further hosts a power-sink device and a power-source device. The bus board, as a secondary PCB, may be surface-mounted on a back side of the primary PCB opposite the power source and sink devices, which are mounted on the front side of the primary PCB. The bus board need only be dimensioned so as to bridge a length between first and second back-side regions of the primary PCB that are further coupled to a portion of the front-side pads employed by the power-sink device. The secondary PCB may be purpose-built for conveying power between the source and sink devices, and include, for example, short, wide traces, that may be formed from multiple heavyweight metallization layers.