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    Endurance aware data placement in storage system with multiple types of media
    22.
    发明授权
    Endurance aware data placement in storage system with multiple types of media 有权

    公开(公告)号：US12093563B2

    公开(公告)日：2024-09-17

    申请号：US17084301

    申请日：2020-10-29

    Applicant: Intel Corporation

    Inventor： Kapil Karkra ,  Mariusz Barczak ,  Michal Wysoczanski ,  Sanjeev Trika ,  James Guilmart

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0688 ,  G06F2212/7201

    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to manage access to a storage system that includes a first persistent storage device and a second persistent storage device, capture input/output telemetry for a workload on the storage system, determine one or more write reduction factors and one or more write invalidation factors for the workload based on the captured input/output telemetry, and allocate storage for the workload between the first persistent storage device and the second persistent storage device based on the one or more write reduction factors and the one or more write invalidation factors. Other embodiments are disclosed and claimed.

    TEMPORAL GRAPH ANALYTICS ON PERSISTENT MEMORY
    23.
    发明申请
    TEMPORAL GRAPH ANALYTICS ON PERSISTENT MEMORY 有权

    公开(公告)号：US20230027351A1

    公开(公告)日：2023-01-26

    申请号：US17933913

    申请日：2022-09-21

    Applicant: Intel Corporation

    Inventor： Joana Matos Fonseca da Trindade ,  Jawad Khan ,  Sanjeev Trika

    IPC: G06F16/2455 ,  G06F3/06 ,  G06F16/22

    Abstract: Systems, apparatuses and methods may provide for technology that includes a single server to store a portion of a temporal graph to a first memory of the single server, and store a second portion of the temporal graph to a second memory of the single server, wherein an access rate of the first memory is greater than an access rate of the second memory, and wherein a capacity of the second memory is greater than a capacity of the first memory. The single server may also retrieve vertices of the second portion in response to a selectivity of an input query exceeding a cost model threshold.

    CACHE EVICTIONS MANAGEMENT IN A TWO LEVEL MEMORY CONTROLLER MODE
    24.
    发明申请
    CACHE EVICTIONS MANAGEMENT IN A TWO LEVEL MEMORY CONTROLLER MODE 有权

    公开(公告)号：US20220188228A1

    公开(公告)日：2022-06-16

    申请号：US17559870

    申请日：2021-12-22

    Applicant: Intel Corporation

    Inventor： Sanjeev Trika ,  Mark Hildebrand ,  Jawad Khan

    IPC: G06F12/0802

    Abstract: Systems, apparatuses, and methods provide for a memory controller to manage cache evictions and/or insertions in a two level memory controller mode that uses a dynamic random access memory as a transparent cache for a persistent memory. For example, a memory controller includes logic to map cached data in the dynamic random access memory to an original address of copied data in the persistent memory. The cached data in the dynamic random access memory is tracked as to whether it is dirty data or clean data with respect to the copied data in the persistent memory. Upon eviction of the cached data from the dynamic random access memory, a writeback of the cached data that has been evicted to the persistent memory is bypassed when the cached data is tracked as dirty data.

    MULTIPLE TIER STORAGE DEPLOYMENT MANAGEMENT ENGINE
    25.
    发明申请
    MULTIPLE TIER STORAGE DEPLOYMENT MANAGEMENT ENGINE 有权

    公开(公告)号：US20220107733A1

    公开(公告)日：2022-04-07

    申请号：US17551755

    申请日：2021-12-15

    Applicant: Intel Corporation

    Inventor： Sanjeev Trika ,  Kapil Karkra ,  Mariusz Barczak

    IPC: G06F3/06 ,  G06F11/30

    Abstract: An embodiment of an electronic apparatus may comprise a processor, memory communicatively coupled to the processor, and circuitry communicatively coupled to the processor and the memory to determine a group of available types of persistent memory devices and a set of characteristics associated with each type of persistent memory device of the group of available types of persistent memory devices, determine of a set of requirements for a storage system, and determine a deployment configuration for the storage system with a lowest storage acquisition cost based on the group of available types of persistent memory devices, the sets of characteristics, and the set of requirements. Other embodiments are disclosed and claimed.

    Non-volatile file update media
    27.
    发明授权
    Non-volatile file update media 有权

    公开(公告)号：US10884916B2

    公开(公告)日：2021-01-05

    申请号：US15939398

    申请日：2018-03-29

    Applicant: Intel Corporation

    Inventor： Sanjeev Trika ,  Jawad Khan ,  Peng Li ,  Myron Loewen

    IPC: G06F12/02 ,  G06F3/06 ,  G06F21/62 ,  G06F16/16 ,  G06F16/18 ,  G11C13/00

    Abstract: An embodiment of a mass storage apparatus may include first non-volatile media, second non-volatile media which provides a relatively larger write granularity as compared to the first non-volatile media, and logic communicatively coupled to the first and second non-volatile media to direct an access request to one of the first non-volatile media and the second non-volatile media based on an indication from an operating system. An embodiment of a host computing apparatus may include a processor, memory communicatively coupled to the processor, and logic communicatively coupled to the processor to provide an indication for a file system-related access request to a mass storage device based on a granularity size for the file system-related access request. Other embodiments are disclosed and claimed.

    INTELLIGENT PREFETCH DISK-CACHING TECHNOLOGY
    29.
    发明申请
    INTELLIGENT PREFETCH DISK-CACHING TECHNOLOGY 审中-公开

    公开(公告)号：US20190042441A1

    公开(公告)日：2019-02-07

    申请号：US16021677

    申请日：2018-06-28

    Applicant: Intel Corporation

    Inventor： Scott Burridge ,  William Chiu ,  Jawad Khan ,  Sanjeev Trika

    IPC: G06F12/0866

    Abstract: Systems, apparatuses and methods may provide for technology to automatically identify a plurality of non-volatile memory locations associated with a file in response to a close operation with respect to the file and automatically conduct a prefetch from one or more of the plurality of non-volatile memory locations that have been most recently accessed and do not reference cached file segments. The prefetch may be conducted in response to an open operation with respect to the file and on a per-file segment basis.

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