公开(公告)号：US11190460B2

公开(公告)日：2021-11-30

申请号：US16369889

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H04L12/933 ,  H01L25/065 ,  H01L23/538

Abstract: This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.

公开(公告)号：US20190042251A1

公开(公告)日：2019-02-07

申请号：US16146586

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: G06F9/30 ,  G06N3/02 ,  G06F17/50 ,  G05B19/05

Abstract: An integrated circuit device may include programmable logic circuitry on a first integrated circuit die and memory that includes compute-in-memory circuitry on a second die. The programmable logic circuitry may be programmed with a circuit design that operates on a first set of data. The compute-in-memory circuitry of the memory may perform an arithmetic operation using the first set of data from the programmable logic circuitry and a second set of data stored in the memory.

公开(公告)号：US12210873B2

公开(公告)日：2025-01-28

申请号：US18298278

申请日：2023-04-10

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: G06F9/30 ,  G05B19/05 ,  G06F15/78 ,  G06F30/34 ,  G06F30/343 ,  G06F30/347 ,  G06F30/39 ,  G06N3/02

Abstract: An integrated circuit device may include programmable logic circuitry on a first integrated circuit die and memory that includes compute-in-memory circuitry on a second die. The programmable logic circuitry may be programmed with a circuit design that operates on a first set of data. The compute-in-memory circuitry of the memory may perform an arithmetic operation using the first set of data from the programmable logic circuitry and a second set of data stored in the memory.

公开(公告)号：US11562101B2

公开(公告)日：2023-01-24

申请号：US16020805

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Scott J. Weber ,  Sean R. Atsatt ,  Andrew Martyn Draper ,  David Samuel Goldman

IPC: H04L9/30 ,  H04L29/06 ,  G06F21/76 ,  H03M13/27 ,  G06F7/58 ,  G06F21/73

Abstract: A programmable logic device verifies that configuration data permissibly programs the programmable logic device. The programmable logic device includes a programmable fabric having partitions to be programmed by the configuration data, a secure device manager that may generate masks based on the configuration data, and a local sector manager. The masks determine that the configuration data is configured to permissibly program the permitted partitions or that the permitted partitions have been permissibly programmed. The local sector manager applies the masks to generate an interleaved result, compares the interleaved result to an expected result, and sends an indication that the configuration data is configured to permissibly program the permitted partitions or permissibly programmed the permitted partitions in response to determining that the interleaved result is the expected result, or sends an alert to stop programming in response to determining that the interleaved result is not the expected result.

公开(公告)号：US11442889B2

公开(公告)日：2022-09-13

申请号：US16146886

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: G06F15/76 ,  G06N3/08 ,  G06N3/063 ,  G06N3/04

Abstract: Methods and systems for dynamically reconfiguring a deep learning processor by operating the deep learning processor using a first configuration. The deep learning processor then tracking one or more parameters of a deep learning program executed using the deep learning processor in the first configuration. The deep learning processor then reconfigures the deep learning processor to a second configuration to enhance efficiency of the deep learning processor executing the deep learning program based at least in part on the one or more parameters.

公开(公告)号：US11424744B2

公开(公告)日：2022-08-23

申请号：US17094612

申请日：2020-11-10

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  James Ball ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H03K19/1776 ,  G11C5/02 ,  G11C7/10 ,  H01L25/065

Abstract: An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces. The first die and the second die may be coupled using a multi-purpose interface that may allow communication between the first die and the second die. The multi-purpose interface may allow concurrent access to the base die by the programmable logic fabric and the configuration memory by using multiple channels over the multi-purpose interface.

公开(公告)号：US11223361B2

公开(公告)日：2022-01-11

申请号：US16882029

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  James Ball ,  Simon Chong ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu ,  Jun Pin Tan

IPC: H03K19/1776 ,  H03K19/17704 ,  H03K19/17758 ,  H03K19/17768

Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die and having configuration memory. The integrated circuit device may also include a base die that may provide memory and/or operating supporting circuitry. The first die and the second die may be coupled using a high-speed parallel interface. The interface may employ microbumps. The first die and the second die may also include controllers for the interface.

公开(公告)号：US20210058085A1

公开(公告)日：2021-02-25

申请号：US17094612

申请日：2020-11-10

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  James Ball ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H03K19/1776 ,  G11C7/10 ,  H01L25/065 ,  G11C5/02

Abstract: An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces. The first die and the second die may be coupled using a multi-purpose interface that may allow communication between the first die and the second die. The multi-purpose interface may allow concurrent access to the base die by the programmable logic fabric and the configuration memory by using multiple channels over the multi-purpose interface.

公开(公告)号：US10860760B2

公开(公告)日：2020-12-08

申请号：US15941983

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Thiam Khean Hah ,  Vamsi Nalluri ,  Herman Henry Schmit ,  Scott J. Weber ,  Randy Huang

IPC: G06F30/327 ,  G06F30/34 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: Systems and methods are included for efficiently implementing learned parameter systems (LPSs) on a programmable integrated circuit (PIC) via a computing engine. The computing engine receives an input set of learned parameters corresponding to use instances of an LPS. The computing engine reduces at least some redundancies and/or unnecessary operations using instance specific parameter values of the LPS, to generate a less redundant set of learned parameters and a corresponding less redundant LPS. The computing engine generates a netlist based on these, which may share computing resources of the PIC across multiple computations in accordance with the less redundant set of learned parameters and the corresponding less redundant LPS. The computing engine then programs the PIC with the netlist. That is, the netlist replaces use instances of at least some of the original learned parameters and its corresponding LPS and is executed instead of the original.

公开(公告)号：US10833679B2

公开(公告)日：2020-11-10

申请号：US16235984

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  James Ball ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H03K19/177 ,  H01L25/00 ,  H03K19/1776 ,  G11C7/10 ,  H01L25/065 ,  G11C5/02

Abstract: An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces. The first die and the second die may be coupled using a multi-purpose interface that may allow communication between the first die and the second die. The multi-purpose interface may allow concurrent access to the base die by the programmable logic fabric and the configuration memory by using multiple channels over the multi-purpose interface.