公开(公告)号：US20230087367A1

公开(公告)日：2023-03-23

申请号：US17481506

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Xiaoxuan Sun ,  Omkar G. Karhade ,  Dingying Xu ,  Sairam Agraharam ,  Xavier Francois Brun

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface with first conductive contacts and an opposing second surface with second conductive contacts, in a first layer; a die attach film (DAF), at the first surface of the first die, including through-DAF vias (TDVs), wherein respective ones of the TDVs are electrically coupled to respective ones of the first conductive contacts; a conductive pillar in the first layer; and a second die, in a second layer on the first layer, wherein the second die is electrically coupled to the second conductive contacts on the second surface of the first die and electrically coupled to the conductive pillar.

公开(公告)号：US20230082706A1

公开(公告)日：2023-03-16

申请号：US17476301

申请日：2021-09-15

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  William J. Lambert ,  Bharat Prasad Penmecha ,  Xavier Francois Brun

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L23/31 ,  H01L23/532

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first redistribution layer (RDL), having a first surface with first conductive contacts having a first pitch between 170 microns and 400 microns, an opposing second surface, and first conductive pathways between the first and second surfaces; a first die and a conductive pillar in a first layer on the first RDL; a second RDL on the first layer, the second RDL having a first surface, an opposing second surface with second conductive contacts having a second pitch between 18 microns and 150 microns, and second conductive pathways between the first and second surfaces; and a second die, in a second layer on the second RDL, electrically coupled to the first conductive contacts via the first conductive pathways, the conductive pillar, the second conductive pathways, and the second conductive contacts.

公开(公告)号：US20220375844A1

公开(公告)日：2022-11-24

申请号：US17328034

申请日：2021-05-24

Applicant: Intel Corporation

Inventor： Xavier Francois Brun ,  Sanka Ganesan ,  Holly Sawyer ,  Timothy A. Gosselin

IPC: H01L23/498 ,  H01L23/14 ,  H01L23/00 ,  H01L21/48

Abstract: An integrated circuit (IC) package, comprising a die having a first set of interconnects of a first pitch, and an interposer comprising an organic substrate having a second set of interconnects of a second pitch. The interposer also includes an inorganic layer over the organic substrate. The inorganic layer comprises conductive traces electrically coupling the second set of interconnects with the first set of interconnects. The die is attached to the interposer by the first set of interconnects. In some embodiments, the interposer further comprises an embedded die. The IC package further comprises a package support having a third set of interconnects of a third pitch, and a second inorganic layer over a surface of the interposer opposite to the die. The second inorganic layer comprises conductive traces electrically coupling the third set of interconnects with the second set of interconnects.

公开(公告)号：US20210305162A1

公开(公告)日：2021-09-30

申请号：US16829396

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US09679798B2

公开(公告)日：2017-06-13

申请号：US14182969

申请日：2014-02-18

Applicant: Tokyo Electron Limited ,  Intel Corporation

Inventor： Yasuharu Iwashita ,  Osamu Hirakawa ,  Yasutaka Soma ,  Takeshi Tamura ,  Kazutaka Noda ,  Xavier Francois Brun ,  Charles Wayne Singleton, Jr.

IPC: B32B38/10 ,  H01L21/683 ,  B32B43/00

CPC classification number: H01L21/6838 ,  B32B43/006 ,  Y10S156/93 ,  Y10S156/941

Abstract: Disclosed is a substrate conveyance apparatus capable of suppressing a substrate from being damaged. The substrate conveyance apparatus includes a plurality of nozzles, and a main body unit. The plurality of nozzles are configured to jet a gas toward a surface of a substrate to hold the substrate in a non-contact manner. The main body unit is provided with the plurality of nozzles. At least surfaces of the plurality of nozzles are formed of a resin.