公开(公告)号：US11817390B2

公开(公告)日：2023-11-14

申请号：US18090795

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5381 ,  H01L23/3185 ,  H01L23/367 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16227

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US11233009B2

公开(公告)日：2022-01-25

申请号：US16832150

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Praneeth Kumar Akkinepally ,  Frank Truong ,  Jason M. Gamba ,  Robert Alan May

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/31

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a microelectronic component embedded in the package substrate, the microelectronic component including: a substrate having a surface, where the substrate includes a conductive pathway and a mold material region at the surface, where the mold material region includes a through-mold via (TMV) electrically coupled to the conductive pathway, and where the mold material region is at the second surface of the package substrate; and a die conductively coupled, at the second surface of the package substrate, to the package substrate and to the TMV of the microelectronic component.

公开(公告)号：US20210391266A1

公开(公告)日：2021-12-16

申请号：US16902768

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Jason M. Gamba ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Omkar G. Karhade ,  Bai Nie ,  Gang Duan ,  Kristof Kuwawi Darmawikarta ,  Wei-Lun Jen

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20210305162A1

公开(公告)日：2021-09-30

申请号：US16829396

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US20240030142A1

公开(公告)日：2024-01-25

申请号：US18375867

申请日：2023-10-02

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5381 ,  H01L23/367 ,  H01L23/3185 ,  H01L23/5386 ,  H01L24/16 ,  H01L23/5384 ,  H01L2224/16227

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US11688692B2

公开(公告)日：2023-06-27

申请号：US17540079

申请日：2021-12-01

Applicant: Intel Corporation

Inventor： Praneeth Kumar Akkinepally ,  Frank Truong ,  Jason M. Gamba ,  Robert Alan May

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/5381 ,  H01L23/3157 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0655

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a microelectronic component embedded in the package substrate, the microelectronic component including: a substrate having a surface, where the substrate includes a conductive pathway and a mold material region at the surface, where the mold material region includes a through-mold via (TMV) electrically coupled to the conductive pathway, and where the mold material region is at the second surface of the package substrate; and a die conductively coupled, at the second surface of the package substrate, to the package substrate and to the TMV of the microelectronic component.

公开(公告)号：US20210391264A1

公开(公告)日：2021-12-16

申请号：US16902959

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Bai Nie ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Haobo Chen ,  Gang Duan ,  Jason M. Gamba ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Tarek A. Ibrahim ,  Rahul N. Manepalli ,  Deepak Vasant Kulkarni ,  Ravindra Vijay Tanikella

IPC: H01L23/538 ,  H01L21/48

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20200066626A1

公开(公告)日：2020-02-27

申请号：US16107655

申请日：2018-08-21

Applicant: Intel Corporation

Inventor： Jason M. Gamba ,  David Unruh ,  Adrian Kemal Bayraktaroglu ,  Thomas S. Heaton

IPC: H01L23/498 ,  H01L21/683 ,  H01L21/48

Abstract: Disclosed herein are pocket structures, materials, and methods for integrated circuit (IC) package supports. For example, in some embodiments, an IC package support may include: an interconnect pocket having sidewalls provided by a dielectric material; and a conductive contact at a bottom of the interconnect pocket, wherein the conductive contact includes a first metal material and a second metal material, the first metal material provides a bottom surface of the interconnect pocket and is in contact with the dielectric material, the second metal material has a different composition than the first metal material, and the second metal material is in contact with the dielectric material.

公开(公告)号：US20230197661A1

公开(公告)日：2023-06-22

申请号：US17555401

申请日：2021-12-18

Applicant: Intel Corporation

Inventor： Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Bai Nie ,  Haobo Chen ,  Jason M. Gamba

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L24/20 ,  H01L24/19 ,  H01L25/0657 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L24/05 ,  H01L2224/0557 ,  H01L24/06 ,  H01L2224/06181 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2924/2075 ,  H01L2224/215 ,  H01L2224/214 ,  H01L2224/221 ,  H01L2225/06513

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface with first conductive contacts and an opposing second surface with second conductive contacts, in a first layer; a first material layer on the first surface of the first die, the first material layer including silicon and nitrogen; a second material layer on the first material layer, the second material layer including a photoimageable dielectric; conductive vias through the first and second material layers, wherein respective ones of the conductive vias are electrically coupled to respective ones of the second conductive contacts on the first die; and a second die in a second layer, wherein the second layer on the first layer, and wherein the second die is electrically coupled to the second conductive contacts on the first die by the conductive vias.

公开(公告)号：US20230134770A1

公开(公告)日：2023-05-04

申请号：US18090795

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.