公开(公告)号：US08477876B2

公开(公告)日：2013-07-02

申请号：US13336576

申请日：2011-12-23

Applicant: Jacques Meyer

Inventor： Jacques Meyer

IPC: H04L27/00

CPC classification number: H04L7/027 ,  H04L7/0029 ,  H04L27/0014 ,  H04L27/2657 ,  H04L27/2662 ,  H04L27/2678 ,  H04L2027/0024

Abstract: A method for searching a digital transmission having unknown carrier and symbol frequencies in a modulated reception signal, includes performing successive trials of several carrier and symbol frequencies, using decreasing values of the symbol frequency, demodulating the reception signal with the tried carrier frequency, filtering the demodulated signal in a band having a width corresponding to the currently tried symbol frequency, and producing samples of the filtered signal. For each currently tried symbol frequency, forming a complex indicator having a real component and an imaginary component established from the successive samples of the filtered signal such that they have cyclostationary properties and that one of the components tends to cancel when the other component tends towards a relative maximum, building the spectrum of the variation of the complex indicator, searching for a singular spike in the spectrum, and determining the real symbol frequency from the frequency of the spike.

Abstract translation: 一种在调制接收信号中搜索具有未知载波和符号频率的数字传输的方法，包括使用符号频率的减小值来对多个载波和符号频率进行连续的试验，用所试过的载波频率对接收信号进行解调， 在具有对应于当前尝试的符号频率的宽度的频带中的解调信号，并且产生滤波信号的采样。 对于每个当前尝试的符号频率，形成具有从滤波信号的连续采样建立的实分量和虚分量的复指标，使得它们具有循环平稳特性，并且当另一分量趋于朝向 构建复杂指标变化的频谱，寻找频谱中的奇异峰值，并从尖峰频率确定实数符号频率。

公开(公告)号：US06570936B1

公开(公告)日：2003-05-27

申请号：US09358868

申请日：1999-07-22

Applicant: Jacques Meyer

Inventor： Jacques Meyer

IPC: H04L2722

CPC classification number: H04L27/2273 ,  H04L2027/003 ,  H04L2027/0046

Abstract: A method for estimating the frequency error of a demodulator for restoring two binary signals carried on two carriers of same frequency but in phase quadrature, including the steps of forming vectors having as components the successive couples of values of the two binary signals; applying to each vector a transform which multiplies by four its angle at least when it is equal to a multiple of &pgr;/4 and which substantially preserves its module; and calculating the average of the transformed vectors. The frequency error is obtained as being the derivative of the angle of the average vector.

Abstract translation: 一种用于估计用于恢复在相同频率但相位正交的两个载波上携带的两个二进制信号的解调器的频率误差的方法，包括以下步骤：形成具有两个二进制信号的连续值的分量的矢量; 向每个向量应用至少当其等于pi / 4的倍数并且基本上保持其模块时的四倍角度的变换; 并计算变换矢量的平均值。 获得频率误差为平均矢量角度的导数。

公开(公告)号：US5890800A

公开(公告)日：1999-04-06

申请号：US948741

申请日：1997-10-10

Applicant: Jacques Meyer

Inventor： Jacques Meyer

IPC: G06F7/72 ,  G06F7/00

CPC classification number: G06F7/726

Abstract: Disclosed is a method and a corresponding circuit to compute the result of the division, in a Galois field of 2.sup.n =N elements, of a first number A by a second number B, these numbers being encoded on n bits, wherein said method comprises the following steps:a--the production of a first intermediate number S(1) encoded on n bits by the squaring of the first number A,b--the production of a second intermediate number R(1) encoded on n bits by the multiplication of the intermediate number S(1) by the number B,c--the performance n-2 times of the steps a and b, the intermediate numbers produced by multiplication R(j) being successively squared, and the intermediate numbers produced by squaring S(j) being successively multiplied by the second number B, andd--the production of the result S(n) by the squaring of the intermediate number R(n-1) produced by the �n-1!th multiplication.

Abstract translation: 公开了一种方法和相应的电路，用于在第二数量B的第一数量A的2n = N个元素的伽罗瓦域中计算分割结果，这些数字被编码在n位上，其中所述方法包括 以下步骤：a-通过第一数字A的平方来生成以n位编码的第一中间数S（1），b-通过乘以N位编码的n位编码的第二中间数R（1）的产生 中间数S（1）乘以B，c-步骤a和b的性能n-2次，由乘法R（j）产生的中间数值相继平方，并且通过平方S（ j）依次乘以第二个数字B，d-通过由第[n-1]次乘法产生的中间数R（n-1）的平方而产生结果S（n）。

公开(公告)号：USRE36090E

公开(公告)日：1999-02-09

申请号：US664229

申请日：1996-06-07

Applicant: Jacques Meyer

Inventor： Jacques Meyer

IPC: H03L7/06 ,  H03L7/099 ,  H03L7/10 ,  H03D3/24

CPC classification number: H03L7/0992 ,  H03L7/10

Abstract: A device synchronizes an internal signal with respect to a reference signal, each signal comprising pulses normally occurring at a rated frequency. The device uses a phase comparator to analyze the phase of the internal signal and the reference signal and produce one logic state if the phase of the internal signal is in advance of the phase of the reference signal and a second logic state otherwise. A programmable frequency divider divides an internal clock signal by a first number if the phase comparator signal produces the first logic state or by a second number if the phase comparator produces the second logic state. A multiplexer provides the programmable divider with either the first number or the second number depending on the logic state produced the phase comparator. The device also includes a storage element for sequentially storing a predetermined number of the latest logic states of the phase comparator. The device also includes circuitry for decrementing the first number when the latest stored logic states of the phase comparator have a single occurrence of the first logic state and for incrementing the second number when the latest stored logic states of the phase comparator have a single occurrence of the second state.

Abstract translation: 一个装置相对于参考信号使内部信号同步，每个信号包括通常以额定频率发生的脉冲。 该器件使用相位比较器来分析内部信号和参考信号的相位，并且如果内部信号的相位超出参考信号的相位而产生一个逻辑状态，否则则产生第二逻辑状态。 如果相位比较器信号产生第一逻辑状态，或者相位比较器产生第二逻辑状态，则可编程分频器将内部时钟信号除以第一数字。 复用器根据产生相位比较器的逻辑状态向可编程分频器提供第一数或第二数。 该装置还包括用于顺序存储相位比较器的预定数量的最新逻辑状态的存储元件。 该装置还包括用于当相位比较器的最新存储的逻辑状态具有第一逻辑状态的单次出现时递减第一数量的电路，并且当相位比较器的最新存储的逻辑状态具有单次发生时，增加第二数量 第二个状态。

公开(公告)号：US5659585A

公开(公告)日：1997-08-19

申请号：US306115

申请日：1994-09-14

Applicant: Jacques Meyer

Inventor： Jacques Meyer

IPC: H03L7/06 ,  H03H17/02 ,  H03H17/04 ,  H03L7/093 ,  H03D3/24 ,  H04B1/10

CPC classification number: H03H17/02

Abstract: A filter uses a digital integrator that establishes the sum, weighted by a coefficient B, of q1-bit input data arriving at a frequency F. The integrator includes a first p-bit shift-right register; a second q-bit shift-right register, circularly connected and storing the current input data in its most significant bits; and a full bit adder having two inputs respectively connected to the outputs of the first and second shift registers, and an output connected to the input of the first shift register. A sequencer enables the shifting of the first register during p clock cycles, and the shifting of the second register during q clock cycles starting b cycles after the beginning of the p cycles, number b being selected as a function of coefficient B.

Abstract translation: 滤波器使用数字积分器，其建立以系数B加权的以频率F到达的q1比特输入数据的和。积分器包括第一p位右移寄存器; 第二个q位移位右寄存器，循环连接并将当前输入数据存储在其最高有效位中; 以及全位加法器，其具有分别连接到第一和第二移位寄存器的输出的两个输入，以及连接到第一移位寄存器的输入的输出。 定序器使得在p个时钟周期期间能够移位第一寄存器，并且在p个周期开始之后的q个时钟周期中b周期之后移位第二寄存器，b被选作系数B的函数。

公开(公告)号：US5563531A

公开(公告)日：1996-10-08

申请号：US306482

申请日：1994-09-15

Applicant: Jacques Meyer

Inventor： Jacques Meyer

IPC: H03L7/06 ,  H03D13/00 ,  H03L7/085 ,  G01R25/00

CPC classification number: H03D13/00 ,  H03L7/085 ,  H03B2200/008

Abstract: A digital phase comparator supplies digital values corresponding to the phase shifts between a first signal having a duty cycle of approximately 0.5 and a second signal. The comparator includes a one-way counter initialized at the frequency of the first signal and clocked by a clock signal having a high frequency with respect to the frequency of the first and second signals. A logic gate enables the counter when the first and second signals are in respective predetermined states. A phase shift is considered to be zero when it corresponds approximately to one half of the counter's capacity.

Abstract translation: 数字相位比较器提供与具有约0.5的占空比的第一信号和第二信号之间的相移相对应的数字值。 比较器包括以第一信号的频率初始化并由相对于第一和第二信号的频率具有高频的时钟信号计时的单向计数器。 当第一和第二信号处于相应的预定状态时，逻辑门使能计数器。 当相当于计数器容量的一半时，相移被认为是零。

公开(公告)号：US5448191A

公开(公告)日：1995-09-05

申请号：US298551

申请日：1994-08-30

Applicant: Jacques Meyer

Inventor： Jacques Meyer

IPC: H03L7/06 ,  H03L7/081 ,  H03L7/099 ,  H03L7/18 ,  H03L7/183 ,  H03L7/197 ,  H03B19/00

CPC classification number: H03L7/0995 ,  H03L7/081 ,  H03L7/183 ,  H03L7/1976

Abstract: A frequency synthesizer provides a synthesized signal. The synthesizer includes an oscillator that supplies a fast clock signal to a divider programmable by a digital data. The most significant bits of the digital data are provided to the programmable divider, and the least significant bits are provided to an accumulator that cooperates with the programmable divider to increment by one unit its division rank when the accumulator overflows. The synthesizer further includes a generator for generating n increasing delay phases of the synthesized signal; a comparator for comparing the content of the accumulator with n ranges of possible increasing values; and circuits for selecting, as the synthesized signal, the phase whose rank corresponds to the rank of the range within which the content of the accumulator is comprised.

Abstract translation: 频率合成器提供合成信号。 合成器包括振荡器，其将快速时钟信号提供给由数字数据可编程的分频器。 数字数据的最高有效位被提供给可编程分频器，并且最低有效位被提供给累加器，该累加器与可编程分频器协作以在累加器溢出时递增一个单位其除法等级。 合成器还包括用于产生合成信号的n个增加延迟相位的发生器; 用于将累加器的内容与可能增加值的n个范围进行比较的比较器; 以及用于选择其等级对应于包含累加器的内容的范围的等级的相位作为合成信号的电路。

公开(公告)号：US5329440A

公开(公告)日：1994-07-12

申请号：US1643

申请日：1993-01-07

Applicant: Jacques Chaussy ,  Jean-Louis Bret ,  Bernard Picot ,  Jacques Meyer

Inventor： Jacques Chaussy ,  Jean-Louis Bret ,  Bernard Picot ,  Jacques Meyer

IPC: G01R19/00 ,  H02M7/537 ,  H02M7/538

CPC classification number: H02M7/537 ,  G01R19/0053 ,  Y10S505/867

Abstract: This device for converting a very-low-amplitude steady voltage signal into an alternating voltage signal, of the type comprising a centre-tapped transformer (1) associated with a transistor (3,4) chopper (2), is characterised in that the transformer (1) and the transistors (3,4) are arranged in a housing (15) held at very low temperature and in which is arranged a material (20) for thermal insulation of the transistors (3,4) with respect to the rest of the housing so as to reduce temperature fluctuations and allow operation of these transistors by self-heating due to their drive current.

Abstract translation: 用于将非常低幅度稳定电压信号转换为包括与晶体管（3,4）斩波器（2）相关联的中心抽头变压器（1）的类型的交流电压信号的该装置的特征在于， 变压器（1）和晶体管（3,4）布置在保持在非常低的温度下的壳体（15）中，并且其中设置有用于相对于晶体管（3,4）的绝热的材料（20） 壳体的其余部分，以便降低温度波动，并允许这些晶体管由于其驱动电流而通过自身加热而工作。

公开(公告)号：US5319681A

公开(公告)日：1994-06-07

申请号：US922331

申请日：1992-07-29

Applicant: Jacques Meyer

Inventor： Jacques Meyer

IPC: H03L7/06 ,  H03L7/099 ,  H03L7/10 ,  H03D3/24

CPC classification number: H03L7/0992 ,  H03L7/10

Abstract: A device synchronizes an internal signal with respect to a reference signal, each signal comprising pulses normally occurring at a rated frequency. The device uses a phase comparator to analyze the phase of the internal signal and the reference signal and produce one logic state if the phase of the internal signal is in advance of the phase of the reference signal and a second logic state otherwise. A programmable frequency divider divides an internal clock signal by a first number if the phase comparator signal produces the first logic state or by a second number if the phase comparator produces the second logic state. A multiplexer provides the programmable divider with either the first number or the second number depending on the logic state produced the phase comparator. The device also includes a storage element for sequentially storing a predetermined number of the latest logic states of the phase comparator. The device also includes circuitry for decrementing the first number when the latest stored logic states of the phase comparator have a single occurrence of the first logic state and for incrementing the second number when the latest stored logic states of the phase comparator have a single occurrence of the second state.

Abstract translation: 一个装置相对于参考信号使内部信号同步，每个信号包括通常以额定频率发生的脉冲。 该器件使用相位比较器来分析内部信号和参考信号的相位，并且如果内部信号的相位超出参考信号的相位而产生一个逻辑状态，否则则产生第二逻辑状态。 如果相位比较器信号产生第一逻辑状态，或者相位比较器产生第二逻辑状态，则可编程分频器将内部时钟信号除以第一数字。 复用器根据产生相位比较器的逻辑状态向可编程分频器提供第一数或第二数。 该装置还包括用于顺序地存储相位比较器的预定数量的最新逻辑状态的存储元件。 该装置还包括用于当相位比较器的最新存储的逻辑状态具有第一逻辑状态的单次出现时递减第一数量的电路，并且当相位比较器的最新存储的逻辑状态具有单次发生时，递增第二数量 第二个状态。

公开(公告)号：US5208212A

公开(公告)日：1993-05-04

申请号：US969648

申请日：1992-10-30

Applicant: Kathleen M. Poss ,  Frederick W. Hotzman ,  Jacques Meyer

Inventor： Kathleen M. Poss ,  Frederick W. Hotzman ,  Jacques Meyer

IPC: A01N39/02 ,  A01N39/04 ,  A01N43/653 ,  A01N47/36 ,  A01P13/00 ,  C07D249/00 ,  C07D249/12

CPC classification number: A01N43/653 ,  C07D249/12

Abstract: This invention relates to compositions comprising 1-aryl-4,5-dihydro-1,2,4-triazol-5(1H)-ones (triazolinones) in combination with the herbicide (2,4-dichlorophenoxy)acetic acid (2,4-D), or like substituted phenoxyalkanoic acids, or esters, or alkali metal or ammonium salts thereof; or with certain herbicidal sulfonylureas, or mixtures of these classes of compounds, to provide herbicidal compositions which are highly effective against a broad array of crop weeds, particularly broadleaf weeds, in crops such as wheat.

Abstract translation: 本发明涉及包含1-芳基-4,5-二氢-1,2,4-三唑-5（1H） - 酮（三唑啉酮）与除草剂（2,4-二氯苯氧基）乙酸（2， 4-D）或类似的取代的苯氧烷酸，或其酯或其碱金属或铵盐; 或具有某些除草磺酰脲类或这些类化合物的混合物，以提供对作物如小麦中广泛的作物杂草，特别是阔叶杂草高度有效的除草组合物。