公开(公告)号：US20110180854A1

公开(公告)日：2011-07-28

申请号：US12657757

申请日：2010-01-27

申请人： Jamal Ramdani

发明人： Jamal Ramdani

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/225 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786

摘要： A method includes forming a relaxed layer in a semiconductor device. The method also includes forming a tensile layer over the relaxed layer, where the tensile layer has tensile stress. The method further includes forming a compressive layer over the relaxed layer, where the compressive layer has compressive stress. The compressive layer has a piezoelectric polarization that is approximately equal to or greater than a spontaneous polarization in the relaxed, tensile, and compressive layers. The piezoelectric polarization in the compressive layer could be in an opposite direction than the spontaneous polarization in the compressive layer. The relaxed layer could include gallium nitride, the tensile layer could include aluminum gallium nitride, and the compressive layer could include aluminum indium gallium nitride.

摘要翻译： 一种方法包括在半导体器件中形成松弛层。 该方法还包括在松弛层上形成拉伸层，其中拉伸层具有拉伸应力。 该方法还包括在松弛层上形成压缩层，其中压缩层具有压应力。 压缩层具有大致等于或大于松弛，拉伸和压缩层中的自发极化的压电极化。 压缩层中的压电极化可能与压缩层中的自发极化方向相反。 松弛层可以包括氮化镓，拉伸层可以包括氮化镓铝，并且压缩层可以包括铝铟镓氮。

公开(公告)号：US20110042778A1

公开(公告)日：2011-02-24

申请号：US12917332

申请日：2010-11-01

申请人： Craig Printy ,  Andre P. Labonte ,  Jamal Ramdani

发明人： Craig Printy ,  Andre P. Labonte ,  Jamal Ramdani

IPC分类号： H01L29/06

CPC分类号： H01L27/1207 ,  H01L21/76264

摘要： One or more trenches can be formed around a first portion of a semiconductor substrate, and an insulating layer can be formed under the first portion of the semiconductor substrate. The one or more trenches and the insulating layer electrically isolate the first portion of the substrate from a second portion of the substrate. The insulating layer can be formed by forming a buried layer in the substrate, such as a silicon germanium layer in a silicon substrate. One or more first trenches through the substrate to the buried layer can be formed, and open spaces can be formed in the buried layer (such as by using an etch selective to silicon germanium over silicon). The one or more first trenches and the open spaces can optionally be filled with insulative material(s). One or more second trenches can be formed and filled to isolate the first portion of the substrate.

摘要翻译： 可以在半导体衬底的第一部分周围形成一个或多个沟槽，并且可以在半导体衬底的第一部分之下形成绝缘层。 一个或多个沟槽和绝缘层将衬底的第一部分与衬底的第二部分电隔离。 可以通过在硅衬底中的诸如硅锗层的衬底中形成掩埋层来形成绝缘层。 可以形成通过衬底到掩埋层的一个或多个第一沟槽，并且可以在掩埋层中形成开放空间（例如通过使用对硅上的硅锗的选择性蚀刻）。 一个或多个第一沟槽和开放空间可以可选地用绝缘材料填充。 可以形成并填充一个或多个第二沟槽以隔离衬底的第一部分。

公开(公告)号：US20100127352A1

公开(公告)日：2010-05-27

申请号：US12692892

申请日：2010-01-25

申请人： Monir El-Diwany ,  Alexei Sadovnikov ,  Jamal Ramdani

发明人： Monir El-Diwany ,  Alexei Sadovnikov ,  Jamal Ramdani

IPC分类号： H01L29/732 ,  H01L29/73

CPC分类号： H01L29/0817 ,  H01L29/66242 ,  H01L29/7378

摘要： A bipolar transistor structure comprises a semiconductor substrate having a first conductivity type, a collector region having a second conductivity type that is opposite the first conductivity type formed in a substrate active device region defined by isolation dielectric material formed in an upper surface of the semiconductor substrate, a base region that includes an intrinsic base region having the first conductivity type formed over the collector region and an extrinsic base region having the second conductivity type formed over the isolation dielectric material, and a sloped in-situ doped emitter plug having the second conductivity type formed on the intrinsic base region.

摘要翻译： 双极晶体管结构包括具有第一导电类型的半导体衬底，具有与在形成于半导体衬底的上表面中的隔离电介质材料限定的衬底有源器件区域中形成的第一导电类型相反的第二导电类型的集电极区域 包括在集电极区域上形成的具有第一导电类型的本征基极区域和形成在隔离电介质材料上的具有第二导电类型的非本征基极区域的基极区域和具有第二导电性的倾斜的原位掺杂发射极插塞 形成在本征基区上。

公开(公告)号：US6121068A

公开(公告)日：2000-09-19

申请号：US47954

申请日：1998-03-26

申请人： Jamal Ramdani ,  Michael S. Lebby ,  Wenbin Jiang

发明人： Jamal Ramdani ,  Michael S. Lebby ,  Wenbin Jiang

IPC分类号： H01S3/02 ,  H01S5/00 ,  H01S5/02 ,  H01S5/183 ,  H01L21/00

CPC分类号： H01S5/1838 ,  H01S5/021 ,  H01S5/0217 ,  H01S5/18341 ,  H01S5/18369

摘要： A longwavelength vertical cavity surface emitting laser (VCSEL) for use in optical telecommunications and method of fabrication that includes the fabrication of an active VCSEL structure on a supporting substrate and the fabrication of a highly reflective DBR mirror structure on a silicon substrate. The DBR mirror structure includes alternating layers of a silicon oxide material and a silicon material fabricated utilizing epitaxially growth techniques and/or wafer bonding using SOI wafer fusion technology. During fabrication of the final VCSEL device, the Si/SiO.sub.2 DBR mirror structure is wafer bonded to the active VCSEL structure. The active VCSEL structure supporting substrate is selectively removed, to enable positioning of a second DBR mirror stack. The final VCSEL device characterized by emitting infra-red light.

摘要翻译： 用于光通信的长波长垂直腔表面发射激光器（VCSEL）和制造方法，其包括在支撑衬底上制造有源VCSEL结构，以及在硅衬底上制造高反射性DBR镜结构。 DBR镜结构包括使用SOI晶片融合技术利用外延生长技术和/或晶片结合制造的氧化硅材料和硅材料的交替层。 在制造最终的VCSEL器件期间，Si / SiO 2 DBR镜结构被晶片结合到有源VCSEL结构。 选择性地去除主动VCSEL结构支撑衬底，以便能够定位第二DBR反射镜堆叠。 最终的VCSEL器件的特征在于发射红外光。

公开(公告)号：US6080690A

公开(公告)日：2000-06-27

申请号：US69591

申请日：1998-04-29

申请人： Michael S. Lebby ,  Karen E. Jachimowicz ,  Jamal Ramdani

发明人： Michael S. Lebby ,  Karen E. Jachimowicz ,  Jamal Ramdani

IPC分类号： A41D31/00 ,  D03D15/00 ,  G01K1/02 ,  H01Q1/27

CPC分类号： G01K1/02 ,  A41D31/00 ,  D03D15/00 ,  D03D15/0066 ,  H01Q1/273 ,  D10B2101/20 ,  D10B2401/16 ,  D10B2401/20 ,  D10B2501/00 ,  Y10T442/3228 ,  Y10T442/3236 ,  Y10T442/3252 ,  Y10T442/339

摘要： A textile fabric including a plurality of electrically conductive fibers and at least one electronic sensor or a plurality of sensing fibers. The textile fabric is intended for fabrication into a functional article of clothing or other item made of the woven textile fabric, so as to increase functionality of the article of clothing or item made thereof. The fabric is intended to assist a wearer in the monitoring of biomedical information and/or environmental conditions existent upon the wearer. The plurality of electrically conductive fibers and sensing devices are characterized as creating an interconnect to a portable electronic monitoring device, integrated components such as heating and cooling bands, electronics, or the like, or for serving as an antenna for signals received and transmitted between an integrated electronic component and a remote monitoring device.

摘要翻译： 一种纺织品，其包括多个导电纤维和至少一个电子传感器或多个感测纤维。 纺织织物旨在制造成由织造织物制成的衣服或其他物品的功能性制品，以增加衣服制品或其制成的物品的功能。 织物旨在帮助佩戴者监测佩戴者上存在的生物医学信息和/或环境条件。 多个导电纤维和感测装置的特征在于形成与便携式电子监视装置的互连，诸如加热和冷却带，电子装置等的集成部件，或用作用于在 集成电子元件和远程监控设备。

公开(公告)号：US5923696A

公开(公告)日：1999-07-13

申请号：US774822

申请日：1996-12-27

申请人： Jamal Ramdani ,  Michael S. Lebby ,  Philip Kiely

发明人： Jamal Ramdani ,  Michael S. Lebby ,  Philip Kiely

IPC分类号： H01S5/00 ,  H01S5/042 ,  H01S5/183 ,  H01S3/19

CPC分类号： H01S5/183 ,  B82Y20/00 ,  H01S5/0421 ,  H01S5/34326

摘要： A stack of distributed Bragg reflectors is disposed on the surface of a semiconductor substrate. The stack includes a plurality of alternating layers of material having alternating refractive indexes with the stack having a first dopant type. A first cladding region is disposed on the stack with an active area disposed on the first cladding region. The active area includes at least two barrier layers and a quantum well layer. A second cladding region is disposed on the active area with a stack of distributed Bragg reflectors disposed on the cladding region. A contact region is disposed on the second stack of distributed Bragg reflectors. The contact region includes a magnesium doped gallium phosphide material.

摘要翻译： 分布式布拉格反射器的堆叠被布置在半导体衬底的表面上。 堆叠包括具有交替折射率的多个交替层的材料，堆叠具有第一掺杂剂类型。 第一包层区域设置在堆叠上，具有设置在第一包层区域上的有源区域。 有源区包括至少两个势垒层和量子阱层。 第二包层区域设置在有源区上，并且布置在包层区域上的分布式布拉格反射器堆叠。 接触区域布置在分布布拉格反射器的第二堆叠上。 接触区域包括掺杂镁的磷化镓材料。

公开(公告)号：US20120119262A1

公开(公告)日：2012-05-17

申请号：US12946305

申请日：2010-11-15

申请人： Wibo Van Noort ,  Jamal Ramdani ,  Andre Labonte ,  Donald Robertson Getchell

发明人： Wibo Van Noort ,  Jamal Ramdani ,  Andre Labonte ,  Donald Robertson Getchell

IPC分类号： H01L29/73 ,  H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/0649 ,  H01L29/1004 ,  H01L29/7371

摘要： A SiGe heterojunction bipolar transistor is fabricated by etching an epitaxially-formed structure to form a mesa that has a collector region, a cap region, and a notched SiGe base region that lies in between. A protective plug is formed in the notch of the SiGe base region so that thick non-conductive regions can be formed on the sides of the collector region and the cap region. Once the non-conductive regions have been formed, the protective plug is removed. An extrinsic base is then formed to lie in the notch and touch the base region, followed by the formation of isolation regions and an emitter region.

摘要翻译： 通过蚀刻外延形成的结构来形成SiGe异质结双极晶体管，以形成具有位于其间的集电极区域，帽区域和缺口SiGe基极区域的台面。 在SiGe基极区域的凹口中形成保护塞，使得可以在集电区域和盖区域的侧面上形成厚的非导电区域。 一旦形成了非导电区域，就去除了保护塞。 然后形成外部碱基以位于凹口中并且接触基极区域，随后形成隔离区域和发射极区域。

公开(公告)号：US08148799B2

公开(公告)日：2012-04-03

申请号：US12692892

申请日：2010-01-25

申请人： Monir El-Diwany ,  Alexei Sadovnikov ,  Jamal Ramdani

发明人： Monir El-Diwany ,  Alexei Sadovnikov ,  Jamal Ramdani

IPC分类号： H01L21/00

CPC分类号： H01L29/0817 ,  H01L29/66242 ,  H01L29/7378

摘要： A bipolar transistor structure comprises a semiconductor substrate having a first conductivity type, a collector region having a second conductivity type that is opposite the first conductivity type formed in a substrate active device region defined by isolation dielectric material formed in an upper surface of the semiconductor substrate, a base region that includes an intrinsic base region having the first conductivity type formed over the collector region and an extrinsic base region having the second conductivity type formed over the isolation dielectric material, and a sloped in-situ doped emitter plug having the second conductivity type formed on the intrinsic base region.

摘要翻译： 双极晶体管结构包括具有第一导电类型的半导体衬底，具有与在形成于半导体衬底的上表面中的隔离电介质材料限定的衬底有源器件区域中形成的第一导电类型相反的第二导电类型的集电极区域 包括在集电极区域上形成的具有第一导电类型的本征基极区域和形成在隔离电介质材料上的具有第二导电类型的非本征基极区域的基极区域和具有第二导电性的倾斜的原位掺杂发射极插塞 形成在本征基区上。

公开(公告)号：US20120056244A1

公开(公告)日：2012-03-08

申请号：US12807336

申请日：2010-09-02

申请人： Sandeep R. Bahl ,  Jamal Ramdani

发明人： Sandeep R. Bahl ,  Jamal Ramdani

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/762 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/7605 ,  H01L23/485 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer.

摘要翻译： 一种方法包括在半导体衬底上形成第一外延层并蚀刻第一外延层以形成多个分离的第一外延区域。 该方法还包括在蚀刻的第一外延层上形成第二外延层。 每个外延层包括至少一个III族氮化物，并且外延层共同形成缓冲器。 该方法还包括在缓冲器上形成器件层，并使用该器件层制造半导体器件。 第二外延层可以包括基本上仅在第一外延区上的第二外延区。 第二外延层还可以覆盖第一外延区域和衬底，并且第二外延层可以被蚀刻也可以不被蚀刻。 可以在用于形成第二外延层的相同操作期间形成器件层。

公开(公告)号：US07838375B1

公开(公告)日：2010-11-23

申请号：US11807215

申请日：2007-05-25

申请人： Mingwei Xu ,  Jamal Ramdani

发明人： Mingwei Xu ,  Jamal Ramdani

IPC分类号： H01L21/331

CPC分类号： H01L29/7378 ,  H01L29/66242

摘要： A system and method are disclosed for providing an improved polyemit module for a self aligned heterojunction bipolar transistor architecture. The polyemit module of the transistor of the present invention is formed using a double layer deposition process. In the double layer deposition process, the first layer is a layer of emitter polysilicon and the second layer is a sacrificial layer of silicon germanium (SiGe). The shape and thickness of the emitter polysilicon layer of the polyemit module provides (1) a reduction in the overall resistance of the emitter and (2) an increase in the contact area between the emitter polysilicon layer and a contact structure that is more than three times the contact area that is provided in prior art polyemit modules.

摘要翻译： 公开了一种用于为自对准异质结双极晶体管结构提供改进的聚合模块的系统和方法。 本发明的晶体管的聚合模块使用双层沉积工艺形成。 在双层沉积工艺中，第一层是发射极多晶硅层，第二层是硅锗牺牲层（SiGe）。 多模块模块的发射极多晶硅层的形状和厚度提供了（1）发射极整体电阻的降低和（2）发射极多晶硅层和接触结构之间的接触面积的增加，该接触面积大于三 倍于现有技术聚合模块中提供的接触面积。