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    STRUCTURED CIRCUIT BOARD AND METHOD
    23.
    发明申请
    STRUCTURED CIRCUIT BOARD AND METHOD 有权
    结构电路板和方法

    公开(公告)号：US20130199834A1

    公开(公告)日：2013-08-08

    申请号：US13807325

    申请日：2011-06-28

    Applicant: Jan De Geest ,  Stefaan Hendrik Jozef Sercu

    Inventor： Jan De Geest ,  Stefaan Hendrik Jozef Sercu

    IPC: H05K1/11

    CPC classification number: H05K1/0251 ,  H05K1/024 ,  H05K1/0245 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/0187 ,  H05K2201/09063 ,  H05K2201/09618 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/10189

    Abstract: A circuit board (1) is provided comprising a plurality of insulating layers, at least one ground layer and at least one layer comprising signal traces. The circuit board comprises at least a first conductive via (17) and a second conductive via (17). The first conductive via and the second conductive via penetrate through at least a first insulating layer of the plurality of insulating layers and are connected to a signal trace. The first conductive via and the second conductive via are arranged adjacent each other. At least in the first insulating layer the first conductive via and the second conductive via are separated in a first direction of separation (R) by a first adjustment portion comprising a dielectric material property different from the first insulating layer.

    Abstract translation: 提供电路板（1），其包括多个绝缘层，至少一个接地层和至少一个包含信号迹线的层。 电路板包括至少第一导电通孔（17）和第二导电通孔（17）。 第一导电通孔和第二导电通孔穿透多个绝缘层中的至少第一绝缘层，并连接到信号迹线。 第一导电通孔和第二导电通孔彼此相邻布置。 至少在第一绝缘层中，通过包括不同于第一绝缘层的介电材料性质的第一调节部分，第一导电通孔和第二导电通孔在第一分离方向（R）分离。

    ELECTRICAL CONNECTOR WITH GROUND PLATES
    24.
    发明申请
    ELECTRICAL CONNECTOR WITH GROUND PLATES 有权
    带接地板的电气连接器

    公开(公告)号：US20110318945A1

    公开(公告)日：2011-12-29

    申请号：US13166081

    申请日：2011-06-22

    Applicant: Jan De Geest ,  Stefaan Hendrik Jozef Sercu ,  Stephen B. Smith ,  Douglas M. Johnescu ,  Jonathan E. Buck

    Inventor： Jan De Geest ,  Stefaan Hendrik Jozef Sercu ,  Stephen B. Smith ,  Douglas M. Johnescu ,  Jonathan E. Buck

    IPC: H01R13/648

    CPC classification number: H01R13/6587 ,  H01R13/2457

    Abstract: An electrical connector and leadframe assemblies for use therein are provided. Each leadframe assembly can be constructed with at least one electric contact having a ground plate. A first type of leadframe assembly includes an uppermost electrical contact defining a ground plate. A second type of leadframe assembly includes a lowermost electrical contact defining a ground plate. The ground plates can reduce the level of crosstalk exhibited by the electrical connector.

    Abstract translation: 提供了一种用于其中的电连接器和引线框架组件。 每个引线框架组件可以构造成具有至少一个具有接地板的电触点。 引线框组件的第一种类型包括限定接地板的最上面的电触点。 第二类引线框架组件包括限定接地板的最下面的电触头。 接地板可以降低电连接器所呈现的串扰水平。

    Matched-impedance surface-mount technology footprints
    26.
    发明授权
    Matched-impedance surface-mount technology footprints 有权
    匹配阻抗表面贴装技术的脚印

    公开(公告)号：US07709747B2

    公开(公告)日：2010-05-04

    申请号：US11287926

    申请日：2005-11-28

    Applicant: Danny L. C. Morlion ,  Stefaan Sercu ,  Winnie Heyvaert ,  Jan De Geest

    Inventor： Danny L. C. Morlion ,  Stefaan Sercu ,  Winnie Heyvaert ,  Jan De Geest

    IPC: H01R12/04 ,  H05K1/11

    CPC classification number: H05K1/114 ,  H05K1/0219 ,  H05K1/0237 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/10189 ,  H05K2201/10734

    Abstract: Disclosed are methodologies for defining matched-impedance surface-mount technology footprints on a substrate such as a printed circuit board, for example, that is adapted to receive an electrical component having an arrangement of terminal leads. Such a footprint may include an arrangement of electrically-conductive pads and an arrangement of electrically-conductive vias. The via arrangement may differ from the pad arrangement. The vias may be arranged to increase routing density, while limiting cross-talk and providing for matched impedance between the component and the substrate. The via arrangement may be altered to achieve a desired routing density on a layer of the board. Increasing the routing density may decrease the number of board layers, which tends to decrease capacitance and thereby increase impedance. Ground vias and signal vias may be arranged with respect to one another in such a manner as to affect impedance. Thus, the via arrangement may be altered to achieve an impedance that matches the impedance of the component. The via arrangement may be also be altered to limit cross-talk among neighboring signal conductors. Thus, the via arrangement may be defined to balance the impedance, cross-talk, and routing density requirements of the system.

    Abstract translation: 公开了用于在诸如印刷电路板的基板上定义匹配阻抗表面贴装技术足迹的方法，例如适于接收具有端子引线布置的电气部件。 这种覆盖区可以包括导电焊盘的布置和导电通孔的布置。 通孔布置可以不同于衬垫布置。 通孔可以被布置成增加布线密度，同时限制串扰并且提供组件和基板之间的匹配阻抗。 可以改变通孔布置以在板的层上实现期望的布线密度。 增加布线密度可能会减少电路板层数，这往往会降低电容，从而增加阻抗。 接地通路和信号通孔可以以影响阻抗的方式相对于彼此布置。 因此，可以改变通孔布置以实现与部件的阻抗匹配的阻抗。 也可以改变通孔装置以限制相邻信号导体之间的串扰。 因此，可以定义通孔布置以平衡系统的阻抗，串扰和布线密度要求。

    Broadside-Coupled Signal Pair Configurations For Electrical Connectors
    27.
    发明申请
    Broadside-Coupled Signal Pair Configurations For Electrical Connectors 有权
    电气连接器的宽边耦合信号对配置

    公开(公告)号：US20080102702A1

    公开(公告)日：2008-05-01

    申请号：US11924002

    申请日：2007-10-25

    Applicant: Stefaan Hendrik Jozef Sercu ,  Jan De Geest ,  Jonathan E. Buck ,  Stephen B. Smith

    Inventor： Stefaan Hendrik Jozef Sercu ,  Jan De Geest ,  Jonathan E. Buck ,  Stephen B. Smith

    IPC: H01R13/648

    CPC classification number: H01R12/724 ,  H01R13/6585

    Abstract: An electrical connector having at least four electrical contacts that form two pairs of differential signal contacts. The first and second electrical contacts may be arranged edge-to-edge along a first direction. The third electrical contact may be adjacent to, and arranged broadside-to-broadside with, the first electrical contact along a second direction substantially transverse to the first direction. The first and third electrical contacts may define one of the pairs of differential signal contacts. The fourth electrical contact may be adjacent to, and arranged broadside-to-broadside with, the second electrical contact along the second direction. The second and fourth electrical contacts may define the other pair of differential signal contacts. The two pairs of differential signal contacts may be offset from one another along the second direction.

    Abstract translation: 具有形成两对差分信号触点的至少四个电触点的电连接器。 第一和第二电触点可以沿着第一方向沿边缘对边缘布置。 第三电触头可以沿着基本上横向于第一方向的第二方向与第一电触头相邻并且布置成宽边到宽边。 第一和第三电触点可以限定差分信号触点对中的一个。 第四电接触可以沿着第二方向与第二电接触相邻并且布置成宽侧到宽边。 第二和第四电触点可以限定另一对差分信号触点。 两对差分信号触点可以沿第二方向彼此偏移。

    Reducing suck-out insertion loss
    28.
    发明授权
    Reducing suck-out insertion loss 有权
    减少吸入插入损耗

    公开(公告)号：US07316585B2

    公开(公告)日：2008-01-08

    申请号：US11626679

    申请日：2007-01-24

    Applicant: Stephen B. Smith ,  Jan De Geest ,  Stefaan Hendrik Jozef Sercu

    Inventor： Stephen B. Smith ,  Jan De Geest ,  Stefaan Hendrik Jozef Sercu

    IPC: H01R13/648

    CPC classification number: H01P3/003

    Abstract: An electrical connector including a lead frame assembly of a first dielectric material that includes a pocket filled with a second dielectric material. A first ground reference, which may be either a ground contact or conductor or a virtual ground defined between signal contacts of a differential signal pair, extends in the first dielectric material and has a first physical length. A second ground reference having a different physical length than the first length extends in the first dielectric material and also through the pocket. The combination of the length of the second ground reference through the pocket along with the difference in the dielectric constants associated with the first and second dielectric materials, provides for equalizing or matching the electrical lengths of these two references having different physical lengths. This may aid in reducing slot-line mode of a co-planar waveguide. The cross-sectional size of the second reference within the pocket may be altered to provide uniform impedance along the length of the second reference as well as an impedance matched to the first conductor.

    Abstract translation: 一种电连接器，包括第一介电材料的引线框架组件，所述引线框架组件包括填充有第二电介质材料的凹穴。 可以是接地触点或导体的第一接地参考或在差分信号对的信号触点之间限定的虚拟接地在第一电介质材料中延伸并且具有第一物理长度。 具有与第一长度不同的物理长度的第二接地参考在第一电介质材料中延伸并且还通过口袋延伸。 通过口袋的第二接地参考的长度与与第一和第二介电材料相关联的介电常数的差异的组合提供均衡或匹配具有不同物理长度的这两个参考物的电长度。 这有助于减小共面波导的槽线模式。 口袋内的第二参考线的横截面尺寸可以改变，以沿着第二参考线的长度提供均匀的阻抗以及与第一导体匹配的阻抗。

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