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107 条记录 (耗时 0.033 秒)

    Multi-Chip Module With Third Dimension Interconnect
    21.
    发明申请
    Multi-Chip Module With Third Dimension Interconnect 审中-公开
    具有三维互连的多芯片模块

    公开(公告)号：US20080256275A1

    公开(公告)日：2008-10-16

    申请号：US12049323

    申请日：2008-03-15

    申请人： Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle

    发明人： Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle

    IPC分类号： G06F13/00

    CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

    摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

    摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。

    System and method for tracking messages between a processing unit and an external device
    22.
    发明授权
    System and method for tracking messages between a processing unit and an external device 有权
    用于跟踪处理单元和外部设备之间的消息的系统和方法

    公开(公告)号：US07836222B2

    公开(公告)日：2010-11-16

    申请号：US10606582

    申请日：2003-06-26

    申请人： Michael Norman Day ,  Brian King Flachs ,  Harm Peter Hofstee ,  Charles Ray Johns ,  John Samuel Liberty

    发明人： Michael Norman Day ,  Brian King Flachs ,  Harm Peter Hofstee ,  Charles Ray Johns ,  John Samuel Liberty

    IPC分类号： G06F3/00 ,  G11C8/00

    CPC分类号： H04Q3/545 ,  H04Q2213/13106

    摘要： An apparatus which uses channel counters in combination with channel count read instructions as a means of providing information that data in a given channel is valid or has not been previously read. The counter may also, in the situation of the channel being defined as blocking, be used to prevent the unintentional overwriting of data in a register used by the channel or, alternatively, prevent further communications with the device assigned to that channel when a given count occurs. Intelligent external devices may also use channel count read instructions sent to the counting mechanism for reading from and writing to the channel.

    摘要翻译： 使用信道计数器与信道计数读取指令组合的装置作为提供给定信道中的数据有效或先前未被读取的信息的手段。 在信道被定义为阻塞的情况下，计数器还可以用于防止在信道使用的寄存器中无意中覆盖数据，或者替代地，当给定计数时，防止与分配给该信道的设备的进一步通信 发生。 智能外部设备还可以使用发送到计数机构的通道计数读取指令来读取和写入通道。

    System for asynchronous DMA command completion notification wherein the DMA command comprising a tag belongs to a plurality of tag groups
    23.
    发明授权
    System for asynchronous DMA command completion notification wherein the DMA command comprising a tag belongs to a plurality of tag groups 失效
    用于异步DMA命令完成通知的系统，其中包括标签的DMA命令属于多个标签组

    公开(公告)号：US07546393B2

    公开(公告)日：2009-06-09

    申请号：US11695436

    申请日：2007-04-02

    申请人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  Peichum Peter Liu ,  Thuong Quang Truong ,  Takeshi Yamazaki

    发明人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  Peichum Peter Liu ,  Thuong Quang Truong ,  Takeshi Yamazaki

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： The present invention provides for a system comprising a DMA queue configured to receive a DMA command comprising a tag, wherein the tag belongs to one of a plurality of tag groups. A counter couples to the DMA queue and is configured to increment a tag group count of the tag group to which the tag belongs upon receipt of the DMA command by the DMA queue and to decrement the tag group count upon execution of the DMA command. A tag group count status register couples to the counter and is configured to store the tag group count for each of the plurality of tag groups. And the tag group count status register is further configured to receive a request for a tag group status and to respond to the request for the tag group status.

    摘要翻译： 本发明提供一种包括配置成接收包括标签的DMA命令的DMA队列的系统，其中标签属于多个标签组之一。 计数器耦合到DMA队列，并配置为在DMA队列接收到DMA命令时增加标签组所属标签组的标签组计数，并在执行DMA命令时递减标签组计数。 标签组计数状态寄存器耦合到计数器，并被配置为存储多个标签组中的每一个的标签组计数。 并且标签组计数状态寄存器被进一步配置为接收对标签组状态的请求并响应对标签组状态的请求。

    Security architecture for system on chip
    24.
    发明授权
    Security architecture for system on chip 有权
    片上系统的安全架构

    公开(公告)号：US08838950B2

    公开(公告)日：2014-09-16

    申请号：US10601374

    申请日：2003-06-23

    申请人： David John Craft ,  Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  John Samuel Liberty

    发明人： David John Craft ,  Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  John Samuel Liberty

    IPC分类号： G06F21/00 ,  H04L9/32 ,  G06F21/53

    CPC分类号： G06F21/53 ,  H04L9/3226 ,  H04L2209/56

    摘要： The present invention provides for authenticating code and/or data and providing a protected environment for execution. The present invention provides for dynamically partitioning and un-partitioning a local store for the authentication of code or data. The local store is partitioned into an isolated and non-isolated section. Code or data is loaded into the isolated section. The code or data is authenticated in the isolated section of the local store. After authentication, the code is executed. After execution, the memory within the isolated region of the attached processor unit is erased, and the attached processor unit de-partitions the isolated section within the local store.

    摘要翻译： 本发明提供了验证代码和/或数据并提供受保护的环境以供执行。 本发明提供了用于对代码或数据的认证的动态分区和分区本地存储。 本地商店被划分成一个隔离和非隔离的部分。 代码或数据被加载到隔离的部分。 代码或数据在本地存储的隔离部分进行身份验证。 认证后，执行代码。 在执行之后，附着的处理器单元的隔离区域内的存储器被擦除，并且附加的处理器单元对本地存储器内的隔离部分进行分区。

    System and method for identifying and accessing streaming data in a locked portion of a cache
    27.
    发明授权
    System and method for identifying and accessing streaming data in a locked portion of a cache 失效
    用于在高速缓存的锁定部分中识别和访问流数据的系统和方法

    公开(公告)号：US06961820B2

    公开(公告)日：2005-11-01

    申请号：US10366440

    申请日：2003-02-12

    申请人： Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Peichun Peter Liu ,  David J. Shippy ,  Thuong Quang Truong

    发明人： Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Peichun Peter Liu ,  David J. Shippy ,  Thuong Quang Truong

    IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F12/12

    CPC分类号： G06F12/126

    摘要： A system and method are provided for efficiently processing data with a cache in a computer system. The computer system has a processor, a cache and a system memory. The processor issues a data request for streaming data. The streaming data has one or more small data portions. The system memory is in communication with the processor. The system memory has a specific area for storing the streaming data. The cache is coupled to the processor. The cache has a predefined area locked for the streaming data. A cache controller is coupled to the cache and is in communication with both the processor and the system memory to transmit at least one small data portion of the streaming data from the specific area of the system memory to the predefined area of the cache when the one small data portion is not found in the predefined area of the cache.

    摘要翻译： 提供了一种系统和方法，用于在计算机系统中用高速缓存高效地处理数据。 计算机系统具有处理器，缓存和系统存储器。 处理器发出流数据的数据请求。 流数据具有一个或多个小数据部分。 系统存储器与处理器通信。 系统存储器具有用于存储流数据的特定区域。 缓存耦合到处理器。 高速缓存具有为流数据锁定的预定义区域。 高速缓存控制器耦合到高速缓存，并且与处理器和系统存储器通信，以将流式数据的至少一个小数据部分从系统存储器的特定区域发送到高速缓存的预定义区域 在缓存的预定义区域中没有找到小数据部分。

    On-chip data transfer in multi-processor system
    28.
    发明授权
    On-chip data transfer in multi-processor system 失效
    多处理器系统中的片上数据传输

    公开(公告)号：US06820143B2

    公开(公告)日：2004-11-16

    申请号：US10322127

    申请日：2002-12-17

    申请人： Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Peichun Peter Liu ,  David Shippy ,  Thuong Quang Truong

    发明人： Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Peichun Peter Liu ,  David Shippy ,  Thuong Quang Truong

    IPC分类号： G06F1328

    CPC分类号： G06F12/0817 ,  G06F12/0897

    摘要： A system and method are provided for improving performance of a computer system by providing a direct data transfer between different processors. The system includes a first and second processor. The first processor is in need of data. The system also includes a directory in communication with the first processor. The directory receives a data request for the data and contains information as to where the data is stored. A cache is coupled to the second processor. An internal bus is coupled between the first processor and the cache to transfer the data from the cache to the first processor when the data is found to be stored in the cache.

    摘要翻译： 提供了一种通过在不同处理器之间提供直接数据传输来提高计算机系统的性能的系统和方法。 该系统包括第一和第二处理器。 第一个处理器需要数据。 该系统还包括与第一处理器通信的目录。 目录接收到数据的数据请求，并包含有关数据存储位置的信息。 缓存耦合到第二处理器。 当发现数据被存储在高速缓存中时，内部总线耦合在第一处理器和高速缓存之间以将数据从高速缓存传送到第一处理器。