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29 条记录 (耗时 0.066 秒)

    Data processing system having data multiplex control apparatus
    21.
    发明授权
    Data processing system having data multiplex control apparatus 失效
    具有数据复用控制装置的数据处理系统

    公开(公告)号：US4300193A

    公开(公告)日：1981-11-10

    申请号：US8003

    申请日：1979-01-31

    申请人： John J. Bradley ,  Robert C. Miller ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

    发明人： John J. Bradley ,  Robert C. Miller ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

    IPC分类号： G06F13/28 ,  G06F3/00

    CPC分类号： G06F13/282

    摘要： In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of information, blocks of information may be transferred between main memory and an input/output controller (IOC) synchronously with operations of the central processor unit (CPU). Logic is provided for enabling one unit of the block of information to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and provides the CPU with a channel number assigned to the requesting IOC. Means are provided within the CPU for determining: the direction of the data transfer, the address of the location of the unit of data to be transferred to/from the main memory, and the number of units of data remaining to be transferred between the main memory and the IOC.

    摘要翻译： 在包括一个或多个公共总线的数据处理系统中，多个输入/输出控制器连接到多个输入/输出控制器用于信息的传送，信息块可以在主存储器和与操作同步的输入/输出控制器（IOC）之间传送 的中央处理器单元（CPU）。 逻辑被提供用于使得在数据复用控制（DMC）数据传送操作期间传送信息块的一个单元，其中请求的IOC请求CPU的DMC数据传送，并向CPU提供分配给 请求IOC。 在CPU内提供用于确定：数据传送的方向，要传送到主存储器的数据单元的位置的地址以及在主存储器之间传输的剩余数据的单元数量 记忆和国际奥委会。

    Dual read/write register file memory
    23.
    发明授权
    Dual read/write register file memory 失效
    双读/写寄存器文件存储器

    公开(公告)号：US4933909A

    公开(公告)日：1990-06-12

    申请号：US286552

    申请日：1988-12-19

    申请人： David E. Cushing ,  Romeo Kharileh ,  Jian-Kuo Shen ,  Ming-Tzer Miu

    发明人： David E. Cushing ,  Romeo Kharileh ,  Jian-Kuo Shen ,  Ming-Tzer Miu

    IPC分类号： G11C11/41 ,  G06F12/00 ,  G11C8/16

    CPC分类号： G11C8/16

    摘要： A dual port read/write register file memory includes means for performing a read/modify write cycle of operation within a single system cycle of operation. The register file memory is constructed from one to more (RAM) addressable multibit storage arrays organized to form a dual read port, single write port RAM. Additionally, the register file includes a plurality of clocked input registers arranged in pairs for storing command, address and data signals for two write ports. The different pairs of registers are connected as inputs to a first set of multiplexer circuits whose outputs connect to the write control signal, address and data inputs of the single write port. The single write port of the register file memory is enabled for writing twice during each cycle. This allows data clocked into the input registers during the previous cycle to be written sequentially into the register file storage locations. By writing data into the input registers instead of the register file memory in a previous cycle, the time required for writing is reduced to a minimum.

    Data processing system having synchronous bus wait/retry cycle
    24.
    发明授权
    Data processing system having synchronous bus wait/retry cycle 失效
    数据处理系统具有同步总线等待/重试周期

    公开(公告)号：US4495571A

    公开(公告)日：1985-01-22

    申请号：US339278

    申请日：1982-01-15

    申请人： Theodore R. Staplin, Jr. ,  John J. Bradley ,  Richard L. King ,  Robert C. Miller ,  Ming T. Miu ,  Jian-Kuo Shen

    发明人： Theodore R. Staplin, Jr. ,  John J. Bradley ,  Richard L. King ,  Robert C. Miller ,  Ming T. Miu ,  Jian-Kuo Shen

    IPC分类号： G06F13/12 ,  G06F13/362 ,  G06F3/04 ,  G06F13/00

    CPC分类号： G06F13/122 ,  G06F13/362

    摘要： A data processing system which includes a central processing unit coupled over a common bus with a plurality of input/output controllers (IOCs) and main memory includes apparatus which allows an IOC to signal the CPU to wait and retry the current I/O instruction. Other apparatus is provided which enables the CPU to continually retry the I/O instruction until the IOC accepts or rejects the I/O instruction and which further allows the CPU to suspend the retrying of the I/O instruction and to process interrupt requests and data transfer requests from any one of the plurality of IOCs. After processing the interrupt or data transfer request, system control is returned to retrying the I/O instruction.

    摘要翻译： 包括通过公共总线与多个输入/输出控制器（IOC）和主存储器耦合的中央处理单元的数据处理系统包括允许IOC发信号通知CPU等待并重试当前I / O指令的装置。 提供了其他设备，使得CPU能够连续地重试I / O指令，直到IOC接受或拒绝I / O指令，并且还允许CPU暂停重试I / O指令并处理中断请求和数据 转移来自多个IOC中的任何一个的请求。 处理中断或数据传输请求后，返回系统控制以重试I / O指令。

    Data processing system having centralized nonexistent memory address detection
    25.
    发明授权
    Data processing system having centralized nonexistent memory address detection 失效
    数据处理系统具有集中的不存在的存储器地址检测

    公开(公告)号：US4340933A

    公开(公告)日：1982-07-20

    申请号：US8010

    申请日：1979-02-12

    申请人： Ming T. Miu ,  John J. Bradley ,  William Panepinto, Jr. ,  Jian-Kuo Shen

    发明人： Ming T. Miu ,  John J. Bradley ,  William Panepinto, Jr. ,  Jian-Kuo Shen

    IPC分类号： G06F12/06 ,  G06F13/362 ,  G06F11/00 ,  G06F13/00

    CPC分类号： G06F13/362 ,  G06F12/0684

    摘要： In a data processing system which includes a central processing unit (CPU) having one or more common buses to which one or more main memory units for storing program software instructions and program data are connected, logic is provided within the CPU for detecting an attempt to access a main memory location not contained in the one or more main memory units present in the data processing system. Logic is provided for detecting the attempt to access the nonexistent memory location for the case where the access was being done in the course of the CPU executing a software instruction or for the case of where the access was being done to transfer data between the main memory and an input/output controller connected to one of the one or more common buses.

    摘要翻译： 在包括具有连接有用于存储程序软件指令和程序数据的一个或多个主存储单元的一个或多个公共总线的中央处理单元（CPU）的数据处理系统中，在CPU内提供逻辑，以检测尝试 访问未包含在数据处理系统中存在的一个或多个主存储器单元中的主存储器位置。 提供逻辑用于检测在CPU执行软件指令的过程中进行访问的情况下的访问不存在的存储器位置的尝试，或者在执行访问以在主存储器之间传送数据的情况下 以及连接到所述一个或多个公共总线中的一个的输入/输出控制器。

    Data processing system having data multiplex control bus cycle
    26.
    发明授权
    Data processing system having data multiplex control bus cycle 失效
    具有数据复用控制总线周期的数据处理系统

    公开(公告)号：US4292668A

    公开(公告)日：1981-09-29

    申请号：US8002

    申请日：1979-01-31

    申请人： Robert C. Miller ,  John J. Bradley ,  Richard L. King ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

    发明人： Robert C. Miller ,  John J. Bradley ,  Richard L. King ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

    IPC分类号： G06F13/28 ,  G06F13/362 ,  G06F3/00

    CPC分类号： G06F13/362 ,  G06F13/285

    摘要： In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processor unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and later provides the CPU with a channel number assigned to the requesting IOC. Means are provided within the system for: resolvng conflicting requests for the one or more common buses, the CPU to acknowledge the DMC request, identifying the requesting IOC to the CPU, accessing one unit of data from main memory or the IOC, and transferring the unit of data to the IOC or main memory.

    摘要翻译： 在包括一个或多个公共总线的数据处理系统中，多个输入/输出控制器连接到该公共总线用于传送数据，数据块可以在主存储器和与操作同步的输入/输出控制器（IOC）之间传送 的中央处理器单元（CPU）。 提供逻辑用于在数据复用控制（DMC）数据传输操作期间传输一个数据单元，其中请求的IOC请求CPU的DMC数据传输，并且稍后向CPU提供分配给请求的IOC的通道号 。 在系统内提供了：解决对一个或多个公共总线的冲突请求，CPU确认DMC请求，识别请求的IOC到CPU，从主存储器或IOC访问一个单元的数据，并传送 数据单位到IOC或主存储器。

    Least recently used replacement level generating apparatus
    28.
    发明授权
    Least recently used replacement level generating apparatus 失效
    最近使用的替换液位发生装置

    公开(公告)号：US4783735A

    公开(公告)日：1988-11-08

    申请号：US810945

    申请日：1985-12-19

    申请人： Ming T. Miu ,  Thomas F. Joyce ,  Jian-Kuo Shen ,  Forrest M. Phillips

    发明人： Ming T. Miu ,  Thomas F. Joyce ,  Jian-Kuo Shen ,  Forrest M. Phillips

    IPC分类号： G06F12/12 ,  G06F12/02

    CPC分类号： G06F12/123

    摘要： A least recently used replacement level generator is constructed to include n number of register stages connected in tandem. A comparison circuit associated with each stage except the last stage compare the contents of that stage with an input level value which is to be loaded into the input stage. In the absence of an identical comparison, each stage generates a shift enable signal which is passed on to the next succeeding stage. An identical comparison inhibits the generation of the shift enable signal. Therefore, when a clock signal is applied to the device, register stages, in the presence of a control signal, cause the input level to be loaded into the input stage while the level contents of the register stages are simultaneously shifted through successive stages including the register stage whose contents are identical to the input level under the control of the shift enable signal. The contents of the output register stage accurately and instantaneously defines the least recently used replacement level for use by a cache memory.

    摘要翻译： 构造最少最近使用的替换电平发生器以包括串联连接的n个寄存器级。 与除最后阶段之外的每个阶段相关联的比较电路将该级的内容与要加载到输入级的输入电平值进行比较。 在没有相同的比较的情况下，每个级产生一个传递到下一个后级的移位使能信号。 相同的比较抑制了移位使能信号的产生。 因此，当时钟信号被施加到器件时，在存在控制信号的情况下，寄存器级使得输入电平被加载到输入级，同时寄存器级的电平内容同时被移位到包括 其寄存器级的内容与在移位使能信号的控制下的输入电平相同。 输出寄存器级的内容准确和瞬时地定义了由缓存存储器使用的最近最少使用的替换级别。

    Microprogrammed system having hardware interrupt apparatus
    29.
    发明授权
    Microprogrammed system having hardware interrupt apparatus 失效
    具有硬件中断装置的微编程系统

    公开(公告)号：US4484271A

    公开(公告)日：1984-11-20

    申请号：US392500

    申请日：1982-06-28

    申请人： Ming T. Miu ,  John J. Bradley ,  Jian-Kuo Shen

    发明人： Ming T. Miu ,  John J. Bradley ,  Jian-Kuo Shen

    IPC分类号： G06F9/26

    CPC分类号： G06F9/268

    摘要： A hardware interrupt apparatus for assigning the microprogrammed control system to the highest priority hardware interrupt requesting service. In a microprogrammed control system having at least one hardware interrupt, the presence of a hardware interrupt request will cause the interruption of the currently executing microprogram at the end of the current microinstruction. The address of the next microinstruction in the interrupted microprogram is saved in a hardware interrupt return address register and the next microinstruction address is generated as a function of the particular hardware interrupt to be serviced. A microprogram dedicated to servicing the particular hardware interrupt is then entered at the hardware interrupt generated next microinstruction address. Logic is provided within each microinstruction to inhibit hardware interrupts. Logic is provided within each microinstruction to indicate that the address of the next microinstruction should be taken from the hardware interrupt return address register, thereby allowing for the resumption of the interrupted microprogram. The hardware interrupt apparatus is further organized such that the entry to a second hardware interrupt service microprogram can be made upon the completion of a first hardware interrupt service microprogram without having to return to the original microprogram interrupted by the first hardware interrupt. Upon completion of the second hardware interrupt microprogram service routine, return can be made to the original microprogram interrupted by the first hardware interrupt.

    摘要翻译： 一种硬件中断装置，用于将微程序控制系统分配给最高优先级的硬件中断请求服务。 在具有至少一个硬件中断的微程序控制系统中，存在硬件中断请求将导致在当前微指令结束时当前执行的微程序的中断。 中断微程序中的下一个微指令的地址被保存在硬件中断返回地址寄存器中，并且根据要维护的特定硬件中断产生下一个微指令地址。 然后在产生下一个微指令地址的硬件中断输入专用于维护特定硬件中断的微程序。 在每个微指令内提供逻辑以禁止硬件中断。 在每个微指令内提供逻辑，以指示下一个微指令的地址应从硬件中断返回地址寄存器中取出，从而允许恢复中断的微程序。 硬件中断装置被进一步组织，使得可以在完成第一硬件中断服务微程序之后进入到第二硬件中断服务微程序，而不必返回到由第一硬件中断中断的原始微程序。 在完成第二个硬件中断微程序服务程序后，可以返回由第一个硬件中断中断的原始微程序。