公开(公告)号：US07977732B2

公开(公告)日：2011-07-12

申请号：US12238476

申请日：2008-09-26

申请人： Jin-Taek Park ,  Won-Seok Jung

发明人： Jin-Taek Park ,  Won-Seok Jung

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11573 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/11565

摘要： Provided are nonvolatile memory devices and methods of forming nonvolatile memory devices. Nonvolatile memory devices include a device isolation layer that defines an active region in a substrate. Nonvolatile memory devices further include a first insulating layer, a nonconductive charge storage pattern, a second insulating layer and a control gate line that are sequentially disposed on the active region. The charge storage pattern includes a horizontal portion and a protrusion disposed on an upper portion of an edge of the horizontal portion.

摘要翻译： 提供了非易失性存储器件和形成非易失性存储器件的方法。 非易失性存储器件包括限定衬底中的有源区的器件隔离层。 非易失性存储器件还包括顺序地设置在有源区上的第一绝缘层，非导电电荷存储图案，第二绝缘层和控制栅极线。 电荷存储图案包括水平部分和设置在水平部分的边缘的上部上的突起。

公开(公告)号：US07872295B2

公开(公告)日：2011-01-18

申请号：US12367988

申请日：2009-02-09

申请人： Jin-Taek Park ,  Young-Woo Park ,  Jang-Hyun You ,  Jung-Dal Choi

发明人： Jin-Taek Park ,  Young-Woo Park ,  Jang-Hyun You ,  Jung-Dal Choi

IPC分类号： H01L29/94

CPC分类号： H01L27/11573 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11592 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel barrier layer may comprise a part of the gate dielectric of the HVTs. The tunnel barrier layer may constitute the entire gate dielectric of the HVTs. The corresponding tunnel barrier layer may be formed between or upon shallow trench isolation (STIs). Therefore, the manufacturing efficiency of a driver chip IC may be increased.

摘要翻译： 集成电路包括闪存单元，以及包括低压晶体管（LVT）和高压晶体管（HVT））的外围电路。 集成电路包括包含SiON，SiN或其它高k材料的隧道势垒层。 隧道势垒层可以包括HVT的栅极电介质的一部分。 隧道势垒层可以构成HVT的整个栅电介质。 相应的隧道势垒层可以形成在浅沟槽隔离（STI）之间或之间。 因此，可以提高驱动器芯片IC的制造效率。

公开(公告)号：US07547942B2

公开(公告)日：2009-06-16

申请号：US11709816

申请日：2007-02-23

申请人： Sang-Hun Jeon ,  Chang-Seok Kang ,  Jung-Dal Choi ,  Jin-Taek Park ,  Woong-Hee Sohn ,  Won-Seok Jung

发明人： Sang-Hun Jeon ,  Chang-Seok Kang ,  Jung-Dal Choi ,  Jin-Taek Park ,  Woong-Hee Sohn ,  Won-Seok Jung

IPC分类号： H01L21/00

CPC分类号： H01L27/11546 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11568 ,  H01L29/518 ,  H01L29/78

摘要： A nonvolatile memory device includes a semiconductor substrate including a cell region and a peripheral circuit region, a cell gate on the cell region, and a peripheral circuit gate on the peripheral circuit region, wherein the cell gate includes a charge storage insulating layer on the semiconductor substrate, a gate electrode on the charge storage insulating layer, and a conductive layer on the gate electrode, and the peripheral circuit gate includes a gate insulating layer on the semiconductor substrate, a semiconductor layer on the gate insulating layer, an ohmic layer on the semiconductor layer, and the conductive layer on the ohmic layer.

摘要翻译： 非易失性存储器件包括：包括单元区域和外围电路区域的半导体衬底，单元区域上的单元栅极和外围电路区域上的外围电路栅极，其中，所述单元栅极包括半导体上的电荷存储绝缘层 基板，电荷存储绝缘层上的栅极电极和栅电极上的导电层，外围电路栅极包括在半导体基板上的栅极绝缘层，栅极绝缘层上的半导体层， 半导体层和欧姆层上的导电层。

公开(公告)号：US20090072298A1

公开(公告)日：2009-03-19

申请号：US12232148

申请日：2008-09-11

申请人： Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park ,  Chung-il Hyun

发明人： Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park ,  Chung-il Hyun

IPC分类号： H01L27/115 ,  H01L21/8246

CPC分类号： H01L21/8236 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573

摘要： An embodiment of a semiconductor device includes a substrate including a cell region and a peripheral region; a cell gate pattern on the cell region; and a peripheral gate pattern on the peripheral region, wherein a first cell insulation layer, a second cell insulation layer, and a third cell insulation layer may be between the substrate and the cell gate pattern, a first peripheral insulation layer, a second peripheral insulation layer, and a third peripheral insulation layer may be between the substrate and the peripheral gate pattern, and the second cell insulation layer and the third cell insulation layer include the same material as the respective second peripheral insulation layer and third peripheral insulation layer.

摘要翻译： 半导体器件的实施例包括：包括单元区域和外围区域的衬底; 单元格区域上的单元格栅图案; 以及周边区域上的外围栅极图案，其中第一电池绝缘层，第二电池绝缘层和第三电池绝缘层可以在衬底和电池栅极图案之间，第一外围绝缘层，第二外围绝缘层 层和第三外围绝缘层可以在基板和外围栅极图案之间，并且第二电池绝缘层和第三电池绝缘层包括与相应的第二外围绝缘层和第三外围绝缘层相同的材料。

公开(公告)号：US07195966B2

公开(公告)日：2007-03-27

申请号：US11011644

申请日：2004-12-14

申请人： Jin-Taek Park ,  Jung-Dal Choi ,  Jung-Young Lee ,  Hyun-Suk Kim

发明人： Jin-Taek Park ,  Jung-Dal Choi ,  Jung-Young Lee ,  Hyun-Suk Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/0629 ,  H01L27/11521 ,  H01L27/11524 ,  Y10S438/97

摘要： Methods of fabricating semiconductor devices are provided. Transistors are provided on a semiconductor substrate. A first interlayer insulating layer is provided on the transistors. A second interlayer insulating layer is provided on the first interlayer insulating layer. The second interlayer insulating layer defines a trench such that at least a portion of an upper surface of the first interlayer insulating layer is exposed. A resistor pattern is provided in the trench such that the at least a portion of the resistor pattern contacts the exposed portion of the first interlayer insulating layer. Related methods are also provided.

摘要翻译： 提供制造半导体器件的方法。 晶体管设置在半导体衬底上。 第一层间绝缘层设置在晶体管上。 在第一层间绝缘层上设置第二层间绝缘层。 第二层间绝缘层限定使第一层间绝缘层的上表面的至少一部分露出的沟槽。 电阻图案设置在沟槽中，使得电阻图案的至少一部分接触第一层间绝缘层的暴露部分。 还提供了相关方法。

公开(公告)号：US08198157B2

公开(公告)日：2012-06-12

申请号：US13236913

申请日：2011-09-20

申请人： Jong-Sun Sel ,  Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park

发明人： Jong-Sun Sel ,  Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park

IPC分类号： H01L21/82 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/44

CPC分类号： G11C16/0483 ,  G11C16/3427

摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Related methods are also discussed.

摘要翻译： 非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，有源区上的第一存储单元串和有源区上的第二存储单元串。 第一存储单元串可以包括与第一地选择线和第一串选择线之间的有源区域交叉的第一多个字线，并且可以在第一多个字线中相邻的字线之间提供约相同的第一间隔。 第二存储单元串可以包括与第二接地选择线和第二串选择线之间的有源区域交叉的第二多个字线，并且可以在相邻的第二多个字线之间提供约相同的第一间隔。 还讨论了相关方法。

公开(公告)号：US20120045890A1

公开(公告)日：2012-02-23

申请号：US13236913

申请日：2011-09-20

申请人： Jong-Sun Sel ,  Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park

发明人： Jong-Sun Sel ,  Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park

IPC分类号： H01L21/28

CPC分类号： G11C16/0483 ,  G11C16/3427

摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Related methods are also discussed.

摘要翻译： 非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，有源区上的第一存储单元串和有源区上的第二存储单元串。 第一存储单元串可以包括与第一地选择线和第一串选择线之间的有源区域交叉的第一多个字线，并且可以在第一多个字线中相邻的字线之间提供约相同的第一间隔。 第二存储单元串可以包括与第二接地选择线和第二串选择线之间的有源区域交叉的第二多个字线，并且可以在相邻的第二多个字线之间提供约相同的第一间隔。 还讨论了相关方法。

公开(公告)号：US08048746B2

公开(公告)日：2011-11-01

申请号：US12979890

申请日：2010-12-28

申请人： Jin-Taek Park ,  Young-Woo Park ,  Jang-Hyun You ,  Jung-Dal Choi

发明人： Jin-Taek Park ,  Young-Woo Park ,  Jang-Hyun You ,  Jung-Dal Choi

IPC分类号： H01L21/336

CPC分类号： H01L27/11573 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11592 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel barrier layer may comprise a part of the gate dielectric of the HVTs. The tunnel barrier layer may constitute the entire gate dielectric of the HVTs. The corresponding tunnel barrier layer may be formed between or upon shallow trench isolation (STIs). Therefore, the manufacturing efficiency of a driver chip IC may be increased.

公开(公告)号：US20110233650A1

公开(公告)日：2011-09-29

申请号：US13152307

申请日：2011-06-03

申请人： Jin-Taek Park ,  Won-Seok Jung

发明人： Jin-Taek Park ,  Won-Seok Jung

IPC分类号： H01L29/792

CPC分类号： H01L27/11573 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/11565

摘要： Provided are nonvolatile memory devices and methods of forming nonvolatile memory devices. Nonvolatile memory devices include a device isolation layer that defines an active region in a substrate. Nonvolatile memory devices further include a first insulating layer, a nonconductive charge storage pattern, a second insulating layer and a control gate line that are sequentially disposed on the active region. The charge storage pattern includes a horizontal portion and a protrusion disposed on an upper portion of an edge of the horizontal portion.

摘要翻译： 提供了非易失性存储器件和形成非易失性存储器件的方法。 非易失性存储器件包括限定衬底中的有源区的器件隔离层。 非易失性存储器件还包括顺序地设置在有源区上的第一绝缘层，非导电电荷存储图案，第二绝缘层和控制栅极线。 电荷存储图案包括水平部分和设置在水平部分的边缘的上部上的突起。

公开(公告)号：US20110079838A1

公开(公告)日：2011-04-07

申请号：US12961678

申请日：2010-12-07

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park ,  Byeong-In Choe

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park ,  Byeong-In Choe

IPC分类号： H01L29/788 ,  H01L29/792

CPC分类号： H01L27/1157 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/42352 ,  H01L29/7851 ,  H01L29/792

摘要： A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.

摘要翻译： 一种制造半导体器件的方法包括：形成鳍状有源区，包括相对的侧壁和从衬底突出的表面，在有源区的表面上形成栅极结构，并执行离子注入工艺以形成源极/漏极 在栅极结构的相对侧的有源区中的区域。 源极/漏极区域分别包括有源区的表面中的第一杂质区域和有源区的相对侧壁中的第二杂质区。 第一杂质区域的掺杂浓度大于第二杂质区域的掺杂浓度。 还讨论了相关设备。