公开(公告)号：US06633838B1

公开(公告)日：2003-10-14

申请号：US09435071

申请日：1999-11-04

申请人： Lakshminarayana Baba Arimilli ,  Michael Stephen Floyd ,  Larry Scott Leitner ,  Kevin F. Reick ,  Jennifer Lane Vargus

发明人： Lakshminarayana Baba Arimilli ,  Michael Stephen Floyd ,  Larry Scott Leitner ,  Kevin F. Reick ,  Jennifer Lane Vargus

IPC分类号： G06F1125

CPC分类号： G06F11/2236

摘要： The system and method of the present invention is embodied in a multi-state on-chip logic analyzer that is preferably integrated into a VLSI circuit. In general, the logic analyzer is preferably coupled to a multilevel trace array for storing event trace data generated by the logic analyzer. Input and output logic coupled to both the trace array and the logic analyzer allows reading or writing from or to the trace array, and programming of trigger and condition criteria for transitioning states within the logic analyzer. The logic analyzer has the capability match one or more programmable trigger events to satisfy one or more programmable conditions. Further, the logic analyzer preferably has the capability to initialize programmable conditions in desired states, and to store event trace data in an on-chip array for trace data reconstruction and analysis. Trace array input and output logic allows reading or writing from or to the trace array, and programming of trigger and condition criteria for transitioning states within the logic analyzer. Further, the trace array input and output logic is preferably accessible at both the wafer and component stage to allow for testing and debugging of the VLSI circuitry.

摘要翻译： 本发明的系统和方法体现在优选集成到VLSI电路中的多状态片上逻辑分析仪中。 通常，逻辑分析器优选地耦合到多级跟踪阵列，用于存储由逻辑分析器生成的事件跟踪数据。 耦合到跟踪阵列和逻辑分析仪的输入和输出逻辑器允许从跟踪数组读取或写入数据，以及对逻辑分析器内的转换状态的触发和条件标准进行编程。 逻辑分析仪具有匹配一个或多个可编程触发事件的能力，以满足一个或多个可编程条件。 此外，逻辑分析器优选地具有在期望状态下初始化可编程条件的能力，并且将事件跟踪数据存储在用于跟踪数据重建和分析的片上阵列中。 跟踪数组输入和输出逻辑允许从跟踪数组读取或写入数据，以及对逻辑分析器内的转换状态的触发和条件标准进行编程。 此外，迹线阵列输入和输出逻辑优选在晶片和元件级可访问以允许对VLSI电路进行测试和调试。

公开(公告)号：US06631463B1

公开(公告)日：2003-10-07

申请号：US09436103

申请日：1999-11-08

申请人： Michael Stephen Floyd ,  James Allan Kahle ,  Hung Qui Le ,  John Anthony Moore ,  Kevin Franklin Reick ,  Edward John Silha

发明人： Michael Stephen Floyd ,  James Allan Kahle ,  Hung Qui Le ,  John Anthony Moore ,  Kevin Franklin Reick ,  Edward John Silha

IPC分类号： G06F900

CPC分类号： G06F9/382 ,  G06F9/3017 ,  G06F9/3802 ,  G06F9/3861

摘要： A method and apparatus for patching a problematic instruction within a pipelined processor in a data processing system is presented. A plurality of instructions are fetched, and the plurality of instructions are matched against at least one match condition to generate a matched instruction. The match conditions may include matching the opcode of an instruction, the pre-decode bits of an instruction, a type of instruction, or other conditions. A matched instruction may be marked using a match bit that accompanies the instruction through the instruction pipeline. The matched instruction is then replaced with an internal opcode or internal instruction that causes the instruction scheduling unit to take a special software interrupt. The problematic instruction is then patched through the execution of a set of instructions that cause the desired logical operation of the problematic instruction.

摘要翻译： 提出了一种用于在数据处理系统中的流水线处理器内修补有问题的指令的方法和装置。 获取多个指令，并且将多个指令与至少一个匹配条件进行匹配以生成匹配的指令。 匹配条件可以包括匹配指令的操作码，指令的预解码位，指令的类型或其他条件。 可以使用伴随指令的匹配位通过指令流水线来标记匹配指令。 匹配的指令被替换为内部操作码或内部指令，使指令调度单元进行特殊的软件中断。 然后通过执行导致有问题的指令的期望的逻辑操作的一组指令来修补有问题的指令。

公开(公告)号：US06587963B1

公开(公告)日：2003-07-01

申请号：US09569547

申请日：2000-05-12

申请人： Michael Stephen Floyd ,  Kevin F. Reick

发明人： Michael Stephen Floyd ,  Kevin F. Reick

IPC分类号： H02H305

CPC分类号： G06F11/073 ,  G06F11/0757 ,  G06F11/079

摘要： A method of detecting a hang in a computer system, by generating a plurality of hang strobe signals, detecting that a hang has occurred in the computer system using the hang strobe signals, and determining whether the hang occurred in the processing unit or in the memory subsystem. The intervals of the hang strobe signals may be programmably set. The first hang strobe signal (for the processing unit) preferably has an interval that is longer than the second hang strobe signal (for the memory subsystem). More than two strobe signals may be provided, e.g., for additional access layers of the memory subsystem. Hang detection may be accomplished in part by calculating a number of hang pulses that have issued during pendency of a processor instruction, and then selectively comparing the number to one of two hang limit values respectively associated with the processing unit and the memory subsystem. This selection may be based on a signal indicating whether any requests are still pending in the memory subsystem. The hang limit values can also be programmably set.

摘要翻译： 一种检测计算机系统中的挂起的方法，通过产生多个挂起选通信号，使用所述挂起选通信号检测在所述计算机系统中发生了挂起，以及确定所述挂起是否发生在所述处理单元或所述存储器中 子系统。 挂起选通信号的间隔可以可编程设置。 第一悬挂选通信号（对于处理单元）优选地具有比第二悬挂选通信号（对于存储器子系统）更长的间隔。 可以提供多于两个的选通信号，例如用于存储器子系统的附加存取层。 悬挂检测可以部分地通过计算在处理器指令的未决期间发出的挂起脉冲的数量，然后选择性地将数字与分别与处理单元和存储器子系统相关联的两个悬挂极限值之一进行比较来实现。 该选择可以基于指示在存储器子系统中是否还有待处理的任何请求的信号。 悬挂极限值也可以可编程设置。

公开(公告)号：US08650413B2

公开(公告)日：2014-02-11

申请号：US12749179

申请日：2010-03-29

申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Michael Stephen Floyd ,  Maria Lorena Pesantez

发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Michael Stephen Floyd ,  Maria Lorena Pesantez

IPC分类号： G06F1/32 ,  G06F1/26 ,  G06F9/00

CPC分类号： G06F1/3203 ,  G06F11/3062 ,  G06F11/3096 ,  Y02D10/126

摘要： The embodiments provide an assigned counter of a first set of counters and stores a value for an activity of a set of activities forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. A power manager manages the first set of counters, receives a set of activities to be monitored for a unit, groups the portion into subsets based on at least one of a frequency of occurrence of each activity and power consumption for each activity, sums the stored values corresponding to each activity in each subset to reach a total value for each subset, multiplies the total value of each subset by factor corresponding to the subset to form a scaled value for each subset, and sums the scaled value of each subset to form a power usage value.

摘要翻译： 这些实施例提供了第一组计数器的分配的计数器，并且存储形成一组存储值的一组活动的活动的值。 该值包括计数乘以活动特有的权重因子。 功率管理器管理第一组计数器，接收一组要监视单元的活动，基于每个活动的发生频率和每个活动的功耗中的至少一个，将该部分分组成子集，将所存储的 对应于每个子集中的每个活动的值以达到每个子集的总值，将每个子集的总值乘以与该子集对应的因子，以形成每个子集的缩放值，并且将每个子集的缩放值相加以形成 电力使用价值。

公开(公告)号：US20120216210A1

公开(公告)日：2012-08-23

申请号：US13459398

申请日：2012-04-30

申请人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

发明人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

IPC分类号： G06F9/50

CPC分类号： G06F9/3851 ,  G06F9/50 ,  G06F11/3419 ,  G06F11/348 ,  G06F2201/88 ,  G06F2201/885

摘要： Processor time accounting is enhanced by per-thread internal resource usage counter circuits that account for usage of processor core resources to the threads that use them. Relative resource use can be determined by detecting events such as instruction dispatches for multiple threads active within the processor, which may include idle threads that are still occupying processor resources. The values of the resource usage counters are used periodically to determine relative usage of the processor core by the multiple threads. If all of the events are for a single thread during a given period, the processor time is allocated to the single thread. If no events occur in the given period, then the processor time can be equally allocated among threads. If multiple threads are generating events, a fractional resource usage can be determined for each thread and the counters may be updated in accordance with their fractional usage.

摘要翻译： 处理器时间计费通过每线程内部资源使用计数器电路来增强，这些计算器电路考虑到使用它们的线程使用处理器核心资源。 可以通过检测诸如在处理器内活动的多个线程的指令分派的事件来确定相对资源的使用，其可以包括仍然占据处理器资源的空闲线程。 周期性地使用资源使用计数器的值来确定多个线程对处理器核心的相对使用。 如果所有事件在给定时间段内都是针对单个线程，则处理器时间被分配给单个线程。 如果在给定的时间段内没有发生任何事件，那么处理器的时间可以在线程之间平均分配。 如果多个线程正在生成事件，则可以为每个线程确定分数资源使用，并且可以根据其分数使用来更新计数器。

公开(公告)号：US08209698B2

公开(公告)日：2012-06-26

申请号：US12579540

申请日：2009-10-15

申请人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

发明人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

IPC分类号： G06F9/46 ,  G06F7/38

CPC分类号： G06F9/3851 ,  G06F9/50 ,  G06F11/3419 ,  G06F11/348 ,  G06F2201/88 ,  G06F2201/885

摘要： Processor time accounting is enhanced by per-thread internal resource usage counter circuits that account for usage of processor core resources to the threads that use them. Relative resource use can be determined by detecting events such as instruction dispatches for multiple threads active within the processor, which may include idle threads that are still occupying processor resources. The values of the resource usage counters are used periodically to determine relative usage of the processor core by the multiple threads. If all of the events are for a single thread during a given period, the processor time is allocated to the single thread. If no events occur in the given period, then the processor time can be equally allocated among threads. If multiple threads are generating events, a fractional resource usage can be determined for each thread and the counters may be updated in accordance with their fractional usage.

摘要翻译： 处理器时间计费通过每线程内部资源使用计数器电路来增强，这些计算器电路考虑到使用它们的线程使用处理器核心资源。 可以通过检测诸如在处理器内活动的多个线程的指令分派等事件来确定相对资源的使用，这可能包括仍占用处理器资源的空闲线程。 周期性地使用资源使用计数器的值来确定多个线程对处理器核心的相对使用。 如果所有事件在给定时间段内都是针对单个线程，则处理器时间被分配给单个线程。 如果在给定的时间段内没有发生任何事件，那么处理器的时间可以在线程之间平均分配。 如果多个线程正在生成事件，则可以为每个线程确定分数资源使用，并且可以根据其分数使用来更新计数器。

公开(公告)号：US08145797B2

公开(公告)日：2012-03-27

申请号：US11960878

申请日：2007-12-20

申请人： Michael Stephen Floyd

发明人： Michael Stephen Floyd

IPC分类号： H04Q1/20

CPC分类号： G06F9/3009 ,  G06F9/3851 ,  G06F9/5027 ,  G06F2209/5018

摘要： A processor supporting thread-execution-state-sensitive supervisory commands provides a mechanism for executing supervisory commands for live threads. The commands may be sent from a service processor or another primary processor in the system or may be supplied by the processor itself through supervisory software control. Since the state of execution of one or more threads may change dynamically within a processor core, an external processor will not know the thread execution state at the time the command operates. The method and apparatus provide a command set and logic that supports selective execution of particular commands directed at “alive” threads (or threads in some other determinable execution state), whereby the command is performed only on resources and/or execution units depending on the actual state of thread execution when the command operates within the processor.

摘要翻译： 支持线程执行状态敏感的监控命令的处理器提供了一种用于执行活动线程的监控命令的机制。 命令可以从系统中的服务处理器或另一主处理器发送，或者可以由处理器本身通过监控软件控制来提供。 由于一个或多个线程的执行状态可能在处理器核心内动态地改变，所以外部处理器将不知道命令操作时的线程执行状态。 该方法和装置提供一种命令集和逻辑，该命令集和逻辑支持选择性执行指向“活着”线程的特定命令（或某些其他可确定的执行状态的线程），由此该命令仅在资源和/或执行单元上执行，这取决于 当命令在处理器内运行时线程执行的实际状态。

公开(公告)号：US20100180081A1

公开(公告)日：2010-07-15

申请号：US12354219

申请日：2009-01-15

申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Miles Robert Dooley ,  Michael Stephen Floyd ,  David Scott Ray ,  Bruce Joseph Ronchetti

发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Miles Robert Dooley ,  Michael Stephen Floyd ,  David Scott Ray ,  Bruce Joseph Ronchetti

IPC分类号： G06F12/08 ,  G06F1/32 ,  G06F12/00

CPC分类号： G06F12/0862 ,  G06F1/3203 ,  G06F12/0897 ,  G06F2212/6022

摘要： A data processing system includes a processor, a unit that includes a multi-level cache, a prefetch system and a memory. The data processing system can operate in a first mode and a second mode. The prefetch system can change behavior in response to a desired power consumption policy set by an external agent or automatically via hardware based on on-chip power/performance thresholds.

摘要翻译： 数据处理系统包括处理器，包括多级缓存，预取系统和存储器的单元。 数据处理系统可以在第一模式和第二模式中操作。 预取系统可以响应于由外部代理设置的所需功耗策略或基于片上功率/性能阈值的硬件自动地改变行为。

公开(公告)号：US20100037233A1

公开(公告)日：2010-02-11

申请号：US12579540

申请日：2009-10-15

申请人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

发明人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

IPC分类号： G06F9/46

CPC分类号： G06F9/3851 ,  G06F9/50 ,  G06F11/3419 ,  G06F11/348 ,  G06F2201/88 ,  G06F2201/885

摘要： Processor time accounting is enhanced by per-thread internal resource usage counter circuits that account for usage of processor core resources to the threads that use them. Relative resource use can be determined by detecting events such as instruction dispatches for multiple threads active within the processor, which may include idle threads that are still occupying processor resources. The values of the resource usage counters are used periodically to determine relative usage of the processor core by the multiple threads. If all of the events are for a single thread during a given period, the processor time is allocated to the single thread. If no events occur in the given period, then the processor time can be equally allocated among threads. If multiple threads are generating events, a fractional resource usage can be determined for each thread and the counters may be updated in accordance with their fractional usage.

摘要翻译： 处理器时间计费通过每线程内部资源使用计数器电路来增强，这些计算器电路考虑到使用它们的线程使用处理器核心资源。 可以通过检测诸如在处理器内活动的多个线程的指令分派等事件来确定相对资源的使用，这可能包括仍占用处理器资源的空闲线程。 周期性地使用资源使用计数器的值来确定多个线程对处理器核心的相对使用。 如果所有事件在给定时间段内都是针对单个线程，则处理器时间被分配给单个线程。 如果在给定的时间段内没有发生任何事件，那么处理器的时间可以在线程之间平均分配。 如果多个线程正在生成事件，则可以为每个线程确定分数资源使用，并且可以根据其分数使用来更新计数器。

公开(公告)号：US07657772B2

公开(公告)日：2010-02-02

申请号：US10366437

申请日：2003-02-13

申请人： Joachim Gerhard Clabes ,  Michael Stephen Floyd ,  Paul David Muench ,  Lawrence Joseph Powell

发明人： Joachim Gerhard Clabes ,  Michael Stephen Floyd ,  Paul David Muench ,  Lawrence Joseph Powell

IPC分类号： G06F1/04 ,  G06F1/14

CPC分类号： H01L27/0248 ,  G01K7/425

摘要： An integrated circuit having a temperature sensitive circuit (TSC) to generate a signal indicative of the substrate temperature near the TSC. The integrated circuit has circuitry configured to receive a TSC signal from at least one TSC and to convert the TSC signal to a signal indicative of the integrated circuit's temperature. The thermal control circuit compares the integrated circuit temperature to a threshold and produces a corrective action signal when the temperature exceeds the threshold. The corrective action signal is provided to corrective action circuitry preferably configured to modify the operation of the IC to reduce the IC temperature in proximity to the corresponding TSC.

摘要翻译： 一种具有温度敏感电路（TSC）的集成电路，用于产生指示TSC附近的衬底温度的信号。 集成电路具有被配置为从至少一个TSC接收TSC信号并且将TSC信号转换成指示集成电路的温度的信号的电路。 热控制电路将集成电路温度与阈值进行比较，并在温度超过阈值时产生校正动作信号。 校正动作信号被提供给校正动作电路，优选地被配置为修改IC的操作以降低接近相应TSC的IC温度。