公开(公告)号：US5893967A

公开(公告)日：1999-04-13

申请号：US884700

申请日：1997-06-30

Applicant: N. Johan Knall ,  Christopher J. Spindt ,  Gabriela S. Chakarova ,  Duane A. Haven ,  John M. Macaulay ,  Roger W. Barton ,  Maria S. Nikolova ,  Peter C. Searson

Inventor： N. Johan Knall ,  Christopher J. Spindt ,  Gabriela S. Chakarova ,  Duane A. Haven ,  John M. Macaulay ,  Roger W. Barton ,  Maria S. Nikolova ,  Peter C. Searson

IPC: B81C1/00 ,  C25F3/14 ,  H01J9/02 ,  C25F3/00

CPC classification number: H01J9/025

Abstract: An impedance-assisted electrochemical method is employed for selectively removing certain material from a structure without significantly electrochemically removing certain other material of the same chemical type as the removed material.

Abstract translation: 采用阻抗辅助电化学方法从结构中选择性地去除某些材料，而不用显着地电化学去除与去除的材料相同的化学类型的某些其它材料。

公开(公告)号：US5827099A

公开(公告)日：1998-10-27

申请号：US568885

申请日：1995-12-07

Applicant: Christopher J. Spindt ,  John M. Macaulay ,  Robert M. Duboc, Jr. ,  Peter C. Searson

Inventor： Christopher J. Spindt ,  John M. Macaulay ,  Robert M. Duboc, Jr. ,  Peter C. Searson

IPC: H01J1/30 ,  H01J1/304 ,  H01J3/02 ,  H01J9/02 ,  H01J29/04 ,  H01J31/12

CPC classification number: B82Y10/00 ,  H01J1/3042 ,  H01J3/022 ,  H01J9/025 ,  H01J2201/30403 ,  H01J2201/30457 ,  H01J2201/319

Abstract: Gated electron emitters are fabricated by processes in which charged particles are passed through a track layer (24, 48, or 144) to form charged-particle tracks (26.sub.1, 50.sub.1, or 146.sub.1). The track layer is etched along the tracks to create open spaces (28.sub.1, 52.sub.1, or 148.sub.1). Electron-emissive elements (30 or 142D) can then be formed at locations respectively centered on the open spaces after which a patterned gate layer (34B, 40B, or 158C) is provided. Alternatively, the open spaces in the track layer can be employed to etch corresponding apertures (54.sub.1) through an underlying non-insulating layer (46) which typically serves as the gate layer. An etch is performed through the apertures to form dielectric open spaces (56.sub.1, 96.sub.1, or 114.sub.1) in an insulating layer (24) that lies below the non-insulating layer. Electron-emissive elements (30B, 30/88D.sub.1, 98/102.sub.1, or 118.sub.1) can subsequently be provided, typically in the dielectric open spaces.

Abstract translation: 门电子发射器通过其中带电粒子通过轨道层（24,48或144）以形成带电粒子轨道（261,501或1461）的工艺制造。 轨道层沿着轨道被蚀刻以创建开放空间（281,521或1481）。 然后可以在分开以开放空间为中心的位置处形成电子发射元件（30或142D），之后设置图案化栅极层（34B，40B或158C）。 或者，轨道层中的开放空间可用于通过通常用作栅极层的下面的非绝缘层（46）蚀刻相应的孔（541）。 通过孔进行蚀刻，以在位于非绝缘层下方的绝缘层（24）中形成介电开放空间（561,961或1141）。 随后可以提供电子发射元件（30B，30 / 88D1,98 / 1011或1181），通常在电介质开放空间中。

公开(公告)号：US5564959A

公开(公告)日：1996-10-15

申请号：US269229

申请日：1994-06-29

Applicant: Christopher J. Spindt ,  John M. Macaulay ,  Robert M. Duboc, Jr. ,  Peter C. Searson

Inventor： Christopher J. Spindt ,  John M. Macaulay ,  Robert M. Duboc, Jr. ,  Peter C. Searson

IPC: H01J1/30 ,  H01J1/304 ,  H01J3/02 ,  H01J9/02 ,  H01J29/04 ,  H01J31/12

CPC classification number: B82Y10/00 ,  H01J1/3042 ,  H01J3/022 ,  H01J9/025 ,  H01J2201/30403 ,  H01J2201/30457 ,  H01J2201/319

Abstract: Gated electron emitters are fabricated by processes in which charged particles are passed through a track layer (24, 48, or 144) to form charged-particle tracks (26.sub.1, 50.sub.1, or 146.sub.1). The track layer is etched along the tracks to create open spaces (28.sub.1, 52.sub.1, or 148.sub.1). Electron-emissive elements (30 or 142D) can then be formed at locations respectively centered on the open spaces after which a patterned gate layer (34B, 40B, or 158C) is provided. Alternatively, the open spaces in the track layer can be employed to etch corresponding apertures (54.sub.1) through an underlying non-insulating layer (46) which typically serves as the gate layer. An etch is performed through the apertures to form dielectric open spaces (56.sub.1, 96.sub.1, or 114.sub.1) in an insulating layer (24) that lies below the non-insulating layer. Electron-emissive elements (30B, 30/88D.sub.1, 98/102.sub.1, or 118.sub.1) can subsequently be provided, typically in the dielectric open spaces.

Abstract translation: 门电子发射器通过其中带电粒子通过轨道层（24,48或144）以形成带电粒子轨道（261,501或1461）的工艺制造。 轨道层沿着轨道被蚀刻以创建开放空间（281,521或1481）。 然后可以在分开以开放空间为中心的位置处形成电子发射元件（30或142D），之后设置图案化栅极层（34B，40B或158C）。 或者，轨道层中的开放空间可用于通过通常用作栅极层的下面的非绝缘层（46）蚀刻相应的孔（541）。 通过孔进行蚀刻，以在位于非绝缘层下方的绝缘层（24）中形成介电开放空间（561,961或1141）。 随后可以提供电子发射元件（30B，30 / 88D1,98 / 1011或1181），通常在电介质开放空间中。

公开(公告)号：US5562516A

公开(公告)日：1996-10-08

申请号：US447470

申请日：1995-05-22

Applicant: Christopher J. Spindt ,  John M. Macaulay

Inventor： Christopher J. Spindt ,  John M. Macaulay

IPC: H01J1/304 ,  H01J3/02 ,  H01J9/02

CPC classification number: B82Y10/00 ,  H01J1/3042 ,  H01J3/022 ,  H01J9/025 ,  H01J2201/30403 ,  H01J2201/30457 ,  H01J2201/319

Abstract: A gated area field emitter is fabricated according to a process in which charged-particle tracks are utilized in creating small electron-emissive elements self-aligned to corresponding gate openings in the gate electrode. The electron-emissive elements can have various shapes, including (a) a pedestal, typically a filament, having a pointed tip, (b) a cone, and (c) a combination of a pedestal and an overlying cone whose base diameter is greater than the pedestal's diameter. Each electron-emissive element can be formed as a highly resistive portion and an overlying electron-emissive portion.

Abstract translation: 门控区域场发射器是根据一种工艺制造的，其中带电粒子轨迹用于产生与栅电极中相应的栅极开口自对准的小电子发射元件。 电子发射元件可以具有各种形状，包括（a）具有尖端的基座（通常为细丝），（b）锥体，和（c）底座和上部锥体的组合，其底部直径较大 比基座的直径。 每个电子发射元件可以形成为高电阻部分和上覆电子发射部分。

公开(公告)号：US5559389A

公开(公告)日：1996-09-24

申请号：US158102

申请日：1993-11-24

Applicant: Christopher J. Spindt ,  John M. Macaulay

Inventor： Christopher J. Spindt ,  John M. Macaulay

IPC: H01J1/304 ,  H01J3/02 ,  H01J9/02 ,  H01J1/30

CPC classification number: B82Y10/00 ,  H01J1/3042 ,  H01J3/022 ,  H01J9/025 ,  H01J2201/30403 ,  H01J2201/30457 ,  H01J2201/319

Abstract: A gated electron-emitting device contains a multiplicity of electron-emissive elements, each formed with a pedestal (98) and an overlying cone (94.sub.1). In each electron-emissive element, the base diameter of the cone is greater than the element, the base diameter of the cone is greater than the diameter of the pedestal. With the pedestal being electrically conductive, the cone may be electrically resistive. Alternatively, each electron-emissive element can be an elongated element (30B) that reaches a maximum diameter at a point between, and spaced apart from, both ends of the element.

Abstract translation: 门控电子发射器件包含多个电子发射元件，每个形成有基座（98）和上覆锥体（941）。 在每个电子发射元件中，锥体的基部直径大于元件，锥体的基部直径大于基座的直径。 当基座导电时，锥体可以是电阻的。 或者，每个电子发射元件可以是细长元件（30B），该元件在该元件的两端之间的点之间达到最大直径，并且间隔开。

公开(公告)号：US07090554B1

公开(公告)日：2006-08-15

申请号：US10603415

申请日：2003-06-24

Applicant: Roger W. Barton ,  Kollengode S. Narayanan ,  Bob L. Mackey ,  John M. Macaulay ,  George B. Hopple ,  Donald R. Schropp, Jr. ,  Michael J. Nystrom ,  Sudhakar Gopalakrishnan ,  Shiyou Pei ,  Xueping Xu

Inventor： Roger W. Barton ,  Kollengode S. Narayanan ,  Bob L. Mackey ,  John M. Macaulay ,  George B. Hopple ,  Donald R. Schropp, Jr. ,  Michael J. Nystrom ,  Sudhakar Gopalakrishnan ,  Shiyou Pei ,  Xueping Xu

IPC: H01J9/00

CPC classification number: H01J9/242 ,  H01J29/028 ,  H01J29/864 ,  H01J31/127 ,  H01J2329/863 ,  H01J2329/8635 ,  H01J2329/864 ,  H01J2329/8645 ,  H01J2329/866

Abstract: A flat-panel display is fabricated by a process in which a spacer (24) having a rough face (54 or 56) is positioned between a pair of plate structure (20 and 22). When electrons strike the spacer, the roughness in the spacer's face causes the number of secondary electrons that escape the spacer to be reduced, thereby alleviating positive charge buildup on the spacer. As a result, the image produced by the display is improved. The spacer facial roughness can be achieved in various ways such as providing suitable depressions (60, 62, 64, 66, 70, 74, or 80) or/and protuberances (82, 84, 88, and 92) along the spacer's face.

Abstract translation: 平板显示器是通过一种方法制造的，其中具有粗糙面（54或56）的间隔物（24）位于一对板结构（20和22）之间。 当电子撞击间隔物时，间隔物表面的粗糙度导致逸出间隔物的二次电子数量减少，从而减轻间隔物上的正电荷积累。 结果，改善了由显示器产生的图像。 间隔件面部粗糙度可以以各种方式实现，例如沿着间隔件的表面提供合适的凹陷（60,62,64,66,70,74或80）或/和突起（82,84,88和92）。

公开(公告)号：US06379210B2

公开(公告)日：2002-04-30

申请号：US09727023

申请日：2000-11-29

Applicant: Xueping Xu ,  George R. Brandes ,  Christopher J. Spindt ,  Colin D. Stanners ,  John M. Macaulay

Inventor： Xueping Xu ,  George R. Brandes ,  Christopher J. Spindt ,  Colin D. Stanners ,  John M. Macaulay

IPC: H01J902

CPC classification number: H01J1/3042 ,  H01J2201/30426 ,  H01J2201/319 ,  H01J2329/00

Abstract: A cathode structure suitable for a flat panel display is provided with coated emitters. The emitters are formed with material, typically nickel, capable of growing to a high aspect ratio. These emitters are then coated with carbon containing material for improving the chemical robustness and reducing the work function. One coating process is a DC plasma deposition process in which acetylene is pumped through a DC plasma reactor to create a DC plasma for coating the cathode structure. An alternative coating process is to electrically deposit raw carbon-based material onto the surface of the emitters, and subsequently reduce the raw carbon-based material to the carbon containing material. Work function of coated emitters is typically reduced by about 0.8 to 1.0 eV.

Abstract translation: 适用于平板显示器的阴极结构设置有涂覆的发射器。 发射体由能够生长到高纵横比的材料（通常为镍）形成。 然后，这些发射体涂覆有含碳材料，以改善化学稳定性并降低功函数。 一个涂覆工艺是DC等离子体沉积工艺，其中将乙炔泵送通过DC等离子体反应器以产生用于涂覆阴极结构的DC等离子体。 另一种涂覆方法是将原始碳基材料电沉积到发射体的表面上，随后将原始的碳基材料还原成含碳材料。 涂覆发射体的功函数通常降低约0.8至1.0eV。

公开(公告)号：US06356014B2

公开(公告)日：2002-03-12

申请号：US08826454

申请日：1997-03-27

Applicant: Xueping Xu ,  George R. Brandes ,  Christopher J. Spindt ,  Colin D. Stanners ,  John M. Macaulay

Inventor： Xueping Xu ,  George R. Brandes ,  Christopher J. Spindt ,  Colin D. Stanners ,  John M. Macaulay

IPC: H01J130

CPC classification number: H01J1/3042 ,  H01J2201/30426 ,  H01J2201/319 ,  H01J2329/00

Abstract: A cathode structure suitable for a flat-panel display contains an emitter layer (213) divided into emitter lines, a plurality of electron emitters (229, 239, or 230) situated over the emitter lines, and a gate layer (215A) having an upper surface spaced largely above the electron emitters. The gate layer has a plurality of gate holes (215B) each corresponding to one of the electron emitters. The cathode structure further includes a carbon-containing layer (340, 240, or 241) coated over the electron emitters and directly on at least part of the upper surface of the gate layer such that at least part of the carbon-containing layer extending along and above the gate layer is exposed.

Abstract translation: 适用于平板显示器的阴极结构包含分为发射极线的发射极层（213），位于发射极线之上的多个电子发射体（229,239或230），以及栅极层（215A），具有 上表面大大高于电子发射体。 栅极层具有多个对应于一个电子发射体的栅极孔（215B）。 阴极结构还包括涂覆在电子发射体上并直接位于栅极层的上表面的至少部分上的含碳层（340,240或241），使得至少部分含碳层沿着 并且栅极层上方露出。

公开(公告)号：US06187603B1

公开(公告)日：2001-02-13

申请号：US08660536

申请日：1996-06-07

Applicant: Duane A. Haven ,  N. Johan Knall ,  Paul N. Ludwig ,  John M. Macaulay

Inventor： Duane A. Haven ,  N. Johan Knall ,  Paul N. Ludwig ,  John M. Macaulay

IPC: H01L2100

CPC classification number: H01J9/025 ,  H01J2329/00

Abstract: An electron-emitting device is fabricated by a process in which particles (46) are distributed over an initial structure. The particles are utilized in defining primary openings (52, 64, or 78) that extend through a primary layer (50A, 62A, or 72) provided over a gate layer (48A, 60A, or 60B) formed over an insulating layer (44) and in defining corresponding gate openings (54, 66, or 80) that extend through the gate layer. The insulating layer is etched through the primary and gate openings to form corresponding dielectric openings (56 or 68) through the insulating layer down to a lower non-insulating region (42). Electron-emissive elements (58A or 70A) are formed over the lower non-insulating region so that each electron-emissive element is at least partially situated in one dielectric opening. Formation of the electron-emissive elements, typically in the shape of cones, normally entails depositing emitter material over the primary layer, through the primary and gate openings, and into the dielectric openings and then removing the primary layer so as to remove any emitter material accumulated over the primary layer.

Abstract translation: 通过其中颗粒（46）分布在初始结构上的过程制造电子发射器件。 这些颗粒用于限定主开口（52,64或78），其延伸穿过形成在绝缘层（44）上的栅极层（48A，60A或60B）上的初级层（50A，62A或72） ）并且限定延伸穿过栅极层的对应的栅极开口（54,66或80）。 通过初级和栅极开口蚀刻绝缘层，以形成穿过绝缘层的相应电介质开口（56或68），直到下部非绝缘区域（42）。 电子发射元件（58A或70A）形成在下部非绝缘区域上，使得每个电子发射元件至少部分地位于一个电介质开口中。 电子发射元件的形成（通常为锥形）通常需要在初级层上通过初级和栅极开口沉积发射极材料，并将其沉积到电介质开口中，然后去除主层以除去任何发射体材料 累积在主层上。

公开(公告)号：US6019658A

公开(公告)日：2000-02-01

申请号：US151924

申请日：1998-09-11

Applicant: Paul N. Ludwig ,  Duane A. Haven ,  John M. Macaulay ,  Christopher J. Spindt ,  James M. Cleeves ,  N. Johan Knall

Inventor： Paul N. Ludwig ,  Duane A. Haven ,  John M. Macaulay ,  Christopher J. Spindt ,  James M. Cleeves ,  N. Johan Knall

IPC: H01J9/02

CPC classification number: H01J9/025 ,  H01J2329/00

Abstract: A gated electron-emitter having a lower non-insulating emitter region (42), an overlying insulating layer (44), and a gate layer (48A, 60A, 60B, 120A, or 180A/184) is fabricated by a process in which particles (46) are distributed over the insulating layer, the gate layer, a primary layer (50A, 62A, or 72) provided over the gate layer, a further layer (74) provided over the primary layer, or a pattern-transfer layer (182). The particles are utilized in defining gate openings (54, 66, 80, 122, or 186/188) through the gate layer. Spacer material is provided along the edges of the gate openings to form spacers (102A, 110A, 124A, 140, or 150B). Dielectric openings (80, 114, 128, 144, or 154) are formed through the insulating layer. The dielectric openings can be created before or after creating the spacers. In either case, emitter material in introduced into either the full dielectric openings, or into the portions of the dielectric openings not covered with spacer material, to form electron-emissive elements (106B, 116B, 130A, 146A, or 156B) typically filamentary in shape.

Abstract translation: 具有较低非绝缘发射极区域（42），上覆绝缘层（44）和栅极层（48A，60A，60B，120A或180A / 184）的门控电子发射器通过以下工艺制造，其中 颗粒（46）分布在绝缘层上，栅极层，设置在栅极层上的主层（50A，62A或72），设置在主层上的另一层（74）或图案转移层 （182）。 这些颗粒用于通过栅极层限定栅极开口（54,66,80,122或186/188）。 间隔材料沿栅极开口的边缘设置以形成间隔物（102A，110A，124A，140或150B）。 通过绝缘层形成电介质开口（80,114,128,144或154）。 可以在产生间隔物之前或之后产生电介质开口。 在任一种情况下，发射体材料被引入到完整电介质开口中，或者被引入未被间隔物材料覆盖的电介质开口部分，以形成电子发射元件（106B，116B，130A，146A或156B），通常为 形状。