公开(公告)号：US20090001451A1

公开(公告)日：2009-01-01

申请号：US12146653

申请日：2008-06-26

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park ,  Byeong-In Choe

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park ,  Byeong-In Choe

IPC分类号： H01L21/336 ,  H01L29/792

CPC分类号： H01L27/1157 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/42352 ,  H01L29/7851 ,  H01L29/792

摘要： A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.

摘要翻译： 一种制造半导体器件的方法包括：形成鳍状有源区，包括相对的侧壁和从衬底突出的表面，在有源区的表面上形成栅极结构，并执行离子注入工艺以形成源极/漏极 在栅极结构的相对侧的有源区中的区域。 源极/漏极区域分别包括有源区的表面中的第一杂质区域和有源区的相对侧壁中的第二杂质区。 第一杂质区域的掺杂浓度大于第二杂质区域的掺杂浓度。 还讨论了相关设备。

公开(公告)号：US20080246073A1

公开(公告)日：2008-10-09

申请号：US12138712

申请日：2008-06-13

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

IPC分类号： H01L29/00

CPC分类号： H01L27/105 ,  B82Y10/00 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568

摘要： Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.

摘要翻译： 形成存储器件的方法包括在包括单元阵列区域和电阻器区域的半导体衬底中形成器件隔离层，器件隔离层延伸到电阻器区域中并在半导体衬底中限定有源区域。 在电阻器区域中的器件隔离层上形成第一导电层。 半导体衬底暴露在电池阵列区域中。 电池绝缘层形成在包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的半导体衬底的一部分上。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分中的单元绝缘层上形成第二导电层。 蚀刻第二导电层以在电池阵列区域中形成电池栅电极，并且同时从电阻器区域去除第二导电层，并且在电阻器区域中蚀刻第一导电层以形成电阻器。

公开(公告)号：US20080105918A1

公开(公告)日：2008-05-08

申请号：US11709816

申请日：2007-02-23

申请人： Sang-Hun Jeon ,  Chang-Seok Kang ,  Jung-Dal Choi ,  Jin-Taek Park ,  Woong-Hee Sohn ,  Won-Seok Jung

发明人： Sang-Hun Jeon ,  Chang-Seok Kang ,  Jung-Dal Choi ,  Jin-Taek Park ,  Woong-Hee Sohn ,  Won-Seok Jung

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11546 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11568 ,  H01L29/518 ,  H01L29/78

摘要： A nonvolatile memory device includes a semiconductor substrate including a cell region and a peripheral circuit region, a cell gate on the cell region, and a peripheral circuit gate on the peripheral circuit region, wherein the cell gate includes a charge storage insulating layer on the semiconductor substrate, a gate electrode on the charge storage insulating layer, and a conductive layer on the gate electrode, and the peripheral circuit gate includes a gate insulating layer on the semiconductor substrate, a semiconductor layer on the gate insulating layer, an ohmic layer on the semiconductor layer, and the conductive layer on the ohmic layer.

摘要翻译： 非易失性存储器件包括：包括单元区域和外围电路区域的半导体衬底，单元区域上的单元栅极和外围电路区域上的外围电路栅极，其中，所述单元栅极包括半导体上的电荷存储绝缘层 基板，电荷存储绝缘层上的栅极电极和栅电极上的导电层，外围电路栅极包括在半导体基板上的栅极绝缘层，栅极绝缘层上的半导体层， 半导体层和欧姆层上的导电层。

公开(公告)号：US20110198685A1

公开(公告)日：2011-08-18

申请号：US13095408

申请日：2011-04-27

申请人： Hyun-Suk Kim ,  Sun-II Shim ,  Chang-Seok Kang ,  Won-Cheol Jeong ,  Jung-Dal Choi ,  Jae-Kwan Park ,  Seung-Hyun Lim ,  Sun-Jung Kim

发明人： Hyun-Suk Kim ,  Sun-II Shim ,  Chang-Seok Kang ,  Won-Cheol Jeong ,  Jung-Dal Choi ,  Jae-Kwan Park ,  Seung-Hyun Lim ,  Sun-Jung Kim

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7881 ,  H01L29/792

摘要： Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.

摘要翻译： 提供了非易失性存储器件，其包括在衬底上的控制栅电极; 在控制栅电极和衬底之间的电荷存储绝缘层; 在电荷存储绝缘层和衬底之间的隧道绝缘层; 电荷存储绝缘层和控制栅电极之间的阻挡绝缘层; 以及隧道绝缘层和阻挡绝缘层之间的材料层，材料层具有构成势阱底部的能级。

公开(公告)号：US07399672B2

公开(公告)日：2008-07-15

申请号：US11375983

申请日：2006-03-15

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

IPC分类号： H01L21/336

CPC分类号： H01L27/105 ,  B82Y10/00 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568

摘要： Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.

摘要翻译： 形成存储器件的方法包括在包括单元阵列区域和电阻器区域的半导体衬底中形成器件隔离层，器件隔离层延伸到电阻器区域中并在半导体衬底中限定有源区域。 在电阻器区域中的器件隔离层上形成第一导电层。 半导体衬底暴露在电池阵列区域中。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分上形成电池绝缘层。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分中的单元绝缘层上形成第二导电层。 蚀刻第二导电层以在电池阵列区域中形成电池栅电极，并且同时从电阻器区域去除第二导电层，并且在电阻器区域中蚀刻第一导电层以形成电阻器。

公开(公告)号：US20060208338A1

公开(公告)日：2006-09-21

申请号：US11375983

申请日：2006-03-15

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

IPC分类号： H01L29/00

CPC分类号： H01L27/105 ,  B82Y10/00 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568

摘要： Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.

摘要翻译： 形成存储器件的方法包括在包括单元阵列区域和电阻器区域的半导体衬底中形成器件隔离层，器件隔离层延伸到电阻器区域中并在半导体衬底中限定有源区域。 在电阻器区域中的器件隔离层上形成第一导电层。 半导体衬底暴露在电池阵列区域中。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分上形成电池绝缘层。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分中的单元绝缘层上形成第二导电层。 蚀刻第二导电层以在电池阵列区域中形成电池栅电极，并且同时从电阻器区域去除第二导电层，并且在电阻器区域中蚀刻第一导电层以形成电阻器。

公开(公告)号：US20110095351A1

公开(公告)日：2011-04-28

申请号：US12980399

申请日：2010-12-29

申请人： Sang-Hun Jeon ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Won-Seok Jung

发明人： Sang-Hun Jeon ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Won-Seok Jung

IPC分类号： H01L29/788

CPC分类号： H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor device includes a device isolation layer in a semiconductor substrate, an active region defined by the device isolation layer, the active region including a main surface and a recess region including a bottom surface that is lower than the main surface, and a gate electrode formed over the recess region, wherein a top surface of the device isolation layer adjacent to the recess region is lower than the bottom surface of the recess region.

摘要翻译： 半导体器件包括在半导体衬底中的器件隔离层，由器件隔离层限定的有源区，包括主表面的有源区和包括低于主表面的底表面的凹陷区，以及栅电极 形成在所述凹部区域上，其中，所述器件隔离层的与所述凹部区域相邻的顶面低于所述凹部区域的底面。

公开(公告)号：US07867883B2

公开(公告)日：2011-01-11

申请号：US12146653

申请日：2008-06-26

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park ,  Byeong-In Choe

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park ,  Byeong-In Choe

IPC分类号： H01L21/425 ,  H01L29/06

CPC分类号： H01L27/1157 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/42352 ,  H01L29/7851 ,  H01L29/792

摘要： A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.

摘要翻译： 一种制造半导体器件的方法包括：形成鳍状有源区，包括相对的侧壁和从衬底突出的表面，在有源区的表面上形成栅极结构，并执行离子注入工艺以形成源极/漏极 在栅极结构的相对侧的有源区中的区域。 源极/漏极区域分别包括有源区的表面中的第一杂质区域和有源区的相对侧壁中的第二杂质区。 第一杂质区域的掺杂浓度大于第二杂质区域的掺杂浓度。 还讨论了相关设备。

公开(公告)号：US07605430B2

公开(公告)日：2009-10-20

申请号：US11474699

申请日：2006-06-23

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are formed. Thus, it may be possible to reduce the likelihood of an undesirable connection between an interconnection layer connected to the source and drain regions and a lower sidewall of the active region so that charge leakage from the interconnection layer to a substrate can be prevented or reduced. The sidewall protection layer may be formed using the device isolation layer. Alternatively, an insulating layer having an etch selectivity with respect to an interlayer insulating layer may be formed on the device isolation layer so as to cover the sidewall of the active region.

摘要翻译： 非易失性存储器件包括半导体衬底和半导体衬底上的器件隔离层。 翅片形有源区形成在器件隔离层的各部分之间。 侧壁保护层形成在形成源区和漏区的鳍状有源区的侧壁上。 因此，可以降低连接到源极和漏极区域的互连层和有源区域的下侧壁之间的不期望的连接的可能性，从而可以防止或减少从互连层到衬底的电荷泄漏。 侧壁保护层可以使用器件隔离层形成。 或者，可以在器件隔离层上形成具有相对于层间绝缘层的蚀刻选择性的绝缘层，以覆盖有源区的侧壁。

公开(公告)号：US20080093656A1

公开(公告)日：2008-04-24

申请号：US11709814

申请日：2007-02-23

申请人： Sang-Hun Jeon ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Won-Seok Jung

发明人： Sang-Hun Jeon ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Won-Seok Jung

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor device includes a device isolation layer in a semiconductor substrate, an active region defined by the device isolation layer, the active region including a main surface and a recess region including a bottom surface that is lower than the main surface, and a gate electrode formed over the recess region, wherein a top surface of the device isolation layer adjacent to the recess region is lower than the bottom surface of the recess region.

摘要翻译： 半导体器件包括在半导体衬底中的器件隔离层，由器件隔离层限定的有源区，包括主表面的有源区和包括低于主表面的底表面的凹陷区，以及栅电极 形成在所述凹部区域上，其中，所述器件隔离层的与所述凹部区域相邻的顶面低于所述凹部区域的底面。