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29 条记录 (耗时 0.028 秒)

    Field-effect transistor having a channel region of a Group III-V compound semiconductor and a Group IV semiconductor
    21.
    发明授权
    Field-effect transistor having a channel region of a Group III-V compound semiconductor and a Group IV semiconductor 失效
    具有III-V族化合物半导体的沟道区和IV族半导体的场效应晶体管

    公开(公告)号：US4556895A

    公开(公告)日：1985-12-03

    申请号：US488878

    申请日：1983-04-26

    申请人： Keiichi Ohata

    发明人： Keiichi Ohata

    IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/267 ,  H01L29/778 ,  H01L29/78 ,  H01L27/02 ,  H01L29/12 ,  H01L29/161

    CPC分类号： H01L29/267 ,  H01L27/0605 ,  H01L29/778 ,  H01L29/7783

    摘要： A field-effect semiconductor device having a channel region formed of two superimposed semiconductor layers, each layer being of a different type semiconductor. As between these two kinds of semiconductors, both the electron affinity and the sum of the electron affinity and the energy gap of one semiconductor is larger than the electron affinity and the sum of the electron affinity and the energy gap of the other semiconductor. This relationship is obtained by forming one of the semiconductor layers of Group III-V compound semiconductor and the other of Group IV semiconductor. The fabrication of the field-effect semiconductor device of this invention into monolithic integrated circuits is also disclosed.

    摘要翻译： 具有由两个叠加的半导体层形成的沟道区域的场效应半导体器件，每个层都是不同类型的半导体。 在这两种半导体之间，电子亲和力和一个半导体的电子亲和力和能隙的和都大于电子亲和力以及电子亲和力和另一半导体的能隙之和。 该关系是通过形成III-V族化合物半导体的半导体层和IV族半导体中的另一个来获得的。 还公开了本发明的场效应半导体器件制成单片集成电路。

    High speed semiconductor device and an optelectronic device
    22.
    发明授权
    High speed semiconductor device and an optelectronic device 失效
    高速半导体器件和光电器件

    公开(公告)号：US5111256A

    公开(公告)日：1992-05-05

    申请号：US457588

    申请日：1989-12-27

    申请人： Keiichi Ohata ,  Hikaru Hida

    发明人： Keiichi Ohata ,  Hikaru Hida

    IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L27/15 ,  H01L29/739 ,  H01L29/778 ,  H01L29/80 ,  H01S5/00 ,  H01S5/042

    CPC分类号： H01L27/15 ,  H01L29/739

    摘要： A semiconductor device comprising a first semiconductor layer, a second semiconductor layer on the first layer, a source electrode and a drain electrode both in contact with the first layer, and a hole or electron injection electrode and a gate electrode both formed on the second layer; wherein the second semiconductor is one that has an electron affinity smaller than the first semiconductor when holes are injected or has a sum of an electron affinity and a band gap greater than the first semiconductor when electrons are injected; and wherein the injection electrode and the gate electrode are placed between the source electrode and the drain electrode in this order. In such device, the current driving capability can easily be increased by controlling the injection amount of holes or electrons and the current modulation can easily be controlled by a small capacitance gate electrode; and so operation at an extra-high frequency and an extra-high speed becomes possible.

    摘要翻译： 一种半导体器件，包括第一层上的第一半导体层，第二半导体层，与第一层接触的源电极和漏电极，以及形成在第二层上的空穴或电子注入电极和栅电极 ; 其中所述第二半导体是当注入空穴时具有小于第一半导体的电子亲和力的第二半导体，或者当注入电子时，具有大于第一半导体的电子亲和力和带隙之和; 并且其中所述注入电极和所述栅电极依次被放置在所述源电极和所述漏电极之间。 在这种装置中，通过控制空穴或电子的注入量可容易地提高电流驱动能力，并且电流调制可以容易地由小电容栅电极控制; 因此可以在超高频和超高速度下进行操作。

    High speed and power transistor
    23.
    发明授权
    High speed and power transistor 失效
    高速和功率晶体管

    公开(公告)号：US4839703A

    公开(公告)日：1989-06-13

    申请号：US102788

    申请日：1987-09-23

    申请人： Keiichi Ohata ,  Hikaru Hida ,  Masaki Ogawa

    发明人： Keiichi Ohata ,  Hikaru Hida ,  Masaki Ogawa

    IPC分类号： H01L29/812 ,  H01L21/331 ,  H01L21/338 ,  H01L29/73 ,  H01L29/737 ,  H01L29/739 ,  H01L29/778 ,  H01L29/80

    CPC分类号： H01L29/739

    摘要： A high speed and high power transistor includes a first layer of a first semiconductor material, a second layer of a second semiconductor material formed on the first layer, the second semiconductor material having a smaller electron affinity than the first semiconductor material, first and second electrode positioned ends of the second layer, respectively, in contact with the first layer, and a control electrode formed on the second layer between the first and second electrodes, the control electrode injecting holes into the second layer in accordance with an input signal to induce an electron channel between the first and second electrodes.

    摘要翻译： 高速和高功率晶体管包括第一半导体材料的第一层，形成在第一层上的第二半导体材料的第二层，具有比第一半导体材料更小的电子亲和力的第二半导体材料，第一和第二电极 分别与第一层接触的第二层的定位端和形成在第一和第二电极之间的第二层上的控制电极，控制电极根据输入信号将孔注入第二层，以诱导 第一和第二电极之间的电子通道。

    Indium-phosphide hetero-MIS-gate field effect transistor
    24.
    发明授权
    Indium-phosphide hetero-MIS-gate field effect transistor 失效
    磷化铟异质MIS栅极场效应晶体管

    公开(公告)号：US4837605A

    公开(公告)日：1989-06-06

    申请号：US130575

    申请日：1987-12-09

    申请人： Kensuke Kasahara ,  Tomohiro Itoh ,  Keiichi Ohata

    发明人： Kensuke Kasahara ,  Tomohiro Itoh ,  Keiichi Ohata

    IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L29/43 ,  H01L29/778 ,  H01L29/80

    CPC分类号： H01L29/432 ,  H01L29/802

    摘要： For improvement in gate leakage current, there is disclosed a hetero-MIS gate type field effect transistor comprising (a) an indium-phosphide semi-insulating substrate, (b) an indium-phosphide active layer formed on a surface of the semi-insulating substrate, (c) an aluminum-gallium-arsenide layer formed on a surface of the indium-phosphide active layer, (d) a metal gate electrode formed on the aluminum-gallium-arsenide layer, and (e) source and drain electrodes formed on the indium-phosphide active layer and located at the both sides of the metal gate electrode, and the aluminum-gallium-arsenide layer has the highest aluminum atom composition at the upper surface portion contacting the metal gate electrode and the lowest aluminum atom composition at the lower surface portion contacting the indium-phosphide active layer, so that a discontinuity takes place between the indium-phosphide active layer and the aluminum-gallium-arsenide layer and a higher Schottky barrier is provided between the aluminum-gallium-arsenide layer and the gate electrode, thereby preventing the field effect transistor from the large gate leakage current.

    摘要翻译： 为了提高栅极泄漏电流，公开了一种异质MIS栅极型场效应晶体管，其包含（a）铟 - 磷化物半绝缘基板，（b）在半绝缘性表面上形成的磷化铟活性层 衬底，（c）在磷化铟活性层的表面上形成的铝 - 砷化镓层，（d）形成在所述铝 - 砷化镓层上的金属栅电极，和（e）形成的源极和漏极 在铟磷化物活性层上并且位于金属栅电极的两侧，并且在与金属栅电极接触的上表面部分处的铝 - 砷化镓层具有最高的铝原子组成，而在 所述下表面部分与所述磷化铟活性层接触，使得在所述磷化铟活性层和所述铝 - 砷化镓层之间发生不连续性，并且在所述铟 - 磷化物活性层之间提供较高肖特基势垒 砷化镓铝层和栅电极，从而防止了场效应晶体管的栅极漏电流较大。

    Process of fabricating a heterojunction field effect transistor
    26.
    发明授权
    Process of fabricating a heterojunction field effect transistor 失效
    制造异质结场效应晶体管的工艺

    公开(公告)号：US5026655A

    公开(公告)日：1991-06-25

    申请号：US410070

    申请日：1989-09-21

    申请人： Keiichi Ohata

    发明人： Keiichi Ohata

    IPC分类号： H01L29/812 ,  H01L21/203 ,  H01L21/337 ,  H01L21/338 ,  H01L29/08 ,  H01L29/205 ,  H01L29/778

    CPC分类号： H01L29/66924 ,  H01L29/0843 ,  H01L29/205 ,  H01L29/7787 ,  Y10S148/029 ,  Y10S148/072 ,  Y10S148/169

    摘要： For improvement in a transit time of electrons, there is disclosed a heterojunction field effect transistor fabricated on a semi-insulating GaAs substrate, comprising a first layer overlying the semi-insulating substrate and formed of a high-purity GaAs, a second layer overlying the first layer and formed of an n-type AlGaAs which is smaller in electron affinity than the high-purity GaAs, a source region penetrating from the first layer into the second layer so as to be in contact with the active channel layer formed in the first layer and formed of an gallium-rich AlGaAs, a drain region, and a gate electrode formed on the second layer, an energy gap takes place between the source region and the first layer due to a lower edge of the conduction band thereof higher in energy level than that of the high-purity GaAs, thereby accelerating electrons supplied from the source region to the active channel layer.

    Heterojunction field effect transistor device and process of fabrication thereof
    27.
    发明授权
    Heterojunction field effect transistor device and process of fabrication thereof 失效
    异质结场效应晶体管器件及其制造工艺

    公开(公告)号：US4893155A

    公开(公告)日：1990-01-09

    申请号：US194370

    申请日：1988-05-16

    申请人： Keiichi Ohata

    发明人： Keiichi Ohata

    IPC分类号： H01L29/812 ,  H01L21/203 ,  H01L21/337 ,  H01L21/338 ,  H01L29/08 ,  H01L29/205 ,  H01L29/778 ,  H01L29/80 ,  H01L29/225

    CPC分类号： H01L29/66924 ,  H01L29/0843 ,  H01L29/205 ,  H01L29/7787 ,  Y10S148/029 ,  Y10S148/072 ,  Y10S148/169

    摘要： For improvement in a transit time of electrons, there is disclosed a heterojunction field effect transistor fabricated on a semi-insulating GaAs substrate, comprising a first layer overlying the semi-insulating substrate and formed of a high-purity GaAs, a second layer overlying the first layer and formed of an n-type AlGaAs which is smaller in electron affinity than the high-purity GaAs, a source region penetrating from the first layer into the second layer so as to be in contact with the active channel layer formed in the first layer and formed of an gallium-rich AlGaAs, a drain region, and a gate electrode formed on the second layer, an energy gap takes place between the source region and the first layer due to a lower edge of the conduction band thereof higher in energy level than that of the high-purity GaAs, thereby accelerating electrons supplied from the source region to the active channel layer.

    摘要翻译： 为了改善电子的传输时间，公开了一种制造在半绝缘GaAs衬底上的异质结场效应晶体管，包括覆盖半绝缘衬底并由高纯度GaAs形成的第一层，第二层覆盖 第一层，并且由比所述高纯度GaAs更小的电子亲和力的n型AlGaAs形成，所述源极区从所述第一层穿透到所述第二层，以与所述第一层中形成的有源沟道层接触 层，并且由形成在第二层上的富镓AlGaAs，漏极区域和栅极电极形成，源区域和第一层之间的能隙由于能量的较高的导带的较低边缘而发生 电平高于高纯度GaAs，从而加速从源极区域供给的有源沟道层的电子。

    Process for manufacturing elastic hard fibers
    28.
    发明授权
    Process for manufacturing elastic hard fibers 失效
    制造弹性硬质纤维的方法

    公开(公告)号：US4006208A

    公开(公告)日：1977-02-01

    申请号：US622953

    申请日：1975-10-16

    申请人： Hirotaka Toba ,  Keiichi Ohata ,  Nagayoshi Tsukane

    发明人： Hirotaka Toba ,  Keiichi Ohata ,  Nagayoshi Tsukane

    IPC分类号： D01F6/66 ,  D01D5/08

    CPC分类号： D01F6/66

    摘要： An elastic hard fiber composed mainly of polyisobutylene oxide and having an elastic recovery ratio of at least 70% from 50% extension and a work recovery ratio of at least 70% from 5% extension, is prepared by extruding molten polyisobutylene oxide at a temperature of from 175.degree. C up to the decomposition temperature thereof, cooling the extrudate rapidly to a temperature of -20.degree. to 70.degree. C, and spinning it at a draw ratio of 50 to 1000.

    摘要翻译： 通过在熔融聚异丁烯氧化物的温度下挤出熔融聚异丁烯氧化物，制备主要由聚异丁烯氧化物组成的弹性硬质纤维，弹性恢复率从50％延伸率至少70％，延伸率从5％延伸至70％ 从175℃至其分解温度，将挤出物快速冷却至-20℃至70℃的温度，并以50至1000的拉伸比纺丝。