公开(公告)号：US20230327012A1

公开(公告)日：2023-10-12

申请号：US18332119

申请日：2023-06-09

申请人： NaMLab gGmbH ,  Technische Universität Dresden

发明人： Stefan SCHMULT ,  Andre WACHOWIAK ,  Alexander RUF

IPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/22 ,  H01L29/225 ,  H01L29/205

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/22 ,  H01L29/225 ,  H01L29/7788

摘要： An electronic circuit having a semiconductor device is provided that includes a heterostructure, the heterostructure including a first layer of a compound semiconductor to which a second layer of a compound semiconductor adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), wherein the 2-dimensional electron gas is not present. In aspects, an electronic circuit having a semiconductor device is provided that includes a III-V heterostructure, the III-V heterostructure including a first layer including GaN to which a second layer adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), and having a purity such that the 2-dimensional electron gas is not present. It is therefore advantageous for the present electronic circuit to be enclosed such that, in operation, no light of wavelengths of less than 400 nm may reach the III-V heterostructure and free charge carriers may be generated by these wavelengths.

公开(公告)号：US11569244B2

公开(公告)日：2023-01-31

申请号：US17199646

申请日：2021-03-12

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Gerben Doornbos ,  Marcus Johannes Henricus Van Dal

IPC分类号： H01L27/108 ,  H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L29/225 ,  H01L29/06

摘要： A memory cell comprises a nanowire structure comprising a channel region and source/drain regions of a transistor. The nanowire structure also comprises as first conductor of a capacitive device as a vertical extension of the nanowire structure.

公开(公告)号：US11158709B2

公开(公告)日：2021-10-26

申请号：US17261309

申请日：2019-07-19

申请人： Cornell University

发明人： Reet Chaudhuri ,  Samuel James Bader ,  Jena Debdeep ,  Huili Grace Xing

IPC分类号： H01L29/778 ,  H01L29/267 ,  H01L29/66 ,  H01L29/04 ,  H01L29/20 ,  H01L29/225 ,  H01L29/205

摘要： The long-missing polarization-induced two-dimensional hole gas is finally observed in undoped Group III nitride semiconductor structures and in undoped Group II or Group III oxide semiconductor structures. Experimental results providing unambiguous proof that a 2D hole gas in GaN grown on AlN does not need acceptor doping, and can be formed entirely by the difference in the internal polarization fields across the semiconductor heterojunction are presented.

公开(公告)号：US20190214468A1

公开(公告)日：2019-07-11

申请号：US16209858

申请日：2018-12-04

申请人： MACOM Technology Solutions Holdings, Inc.

发明人： T. Warren Weeks, JR. ,  Edwin Lanier Piner ,  Thomas Gehrke ,  Kevin J. Linthicum

IPC分类号： H01L29/15 ,  H01L29/205 ,  H01L21/02 ,  H01L33/04 ,  C30B23/02 ,  C30B25/18 ,  C30B29/06 ,  C30B29/68 ,  H01L33/06 ,  H01L29/778 ,  H01L29/78 ,  H01L29/04 ,  H01L29/06 ,  H01L29/201 ,  H01L29/66 ,  H01L33/12 ,  H01L33/00 ,  H01L29/20 ,  H01L29/225 ,  H01L33/32 ,  C30B29/40 ,  C30B25/02

CPC分类号： H01L29/155 ,  C30B23/02 ,  C30B23/025 ,  C30B25/02 ,  C30B25/18 ,  C30B25/183 ,  C30B29/06 ,  C30B29/403 ,  C30B29/406 ,  C30B29/68 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/02598 ,  H01L21/0262 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/225 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/78 ,  H01L33/0066 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/04 ,  H01L33/06 ,  H01L33/12 ,  H01L33/32 ,  Y10T428/24942 ,  Y10T428/26 ,  Y10T428/265

摘要： The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

公开(公告)号：US09461119B2

公开(公告)日：2016-10-04

申请号：US14580064

申请日：2014-12-22

申请人： Infineon Technologies Americas Corp.

发明人： T. Warren Weeks, Jr. ,  Edwin Lanier Piner ,  Thomas Gehrke ,  Kevin J. Linthicum

IPC分类号： H01L29/66 ,  H01L29/15 ,  C30B23/02 ,  C30B25/02 ,  C30B25/18 ,  C30B29/40 ,  H01L21/02 ,  H01L33/00 ,  H01L33/32 ,  H01L29/205 ,  H01L29/225 ,  H01L29/20 ,  H01L33/12 ,  H01L29/04 ,  H01L29/06 ,  H01L29/201 ,  H01L29/78 ,  H01L29/778 ,  H01L33/06

CPC分类号： H01L29/155 ,  C30B23/02 ,  C30B23/025 ,  C30B25/02 ,  C30B25/18 ,  C30B25/183 ,  C30B29/06 ,  C30B29/403 ,  C30B29/406 ,  C30B29/68 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/02598 ,  H01L21/0262 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/225 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/78 ,  H01L33/0066 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/04 ,  H01L33/06 ,  H01L33/12 ,  H01L33/32 ,  Y10T428/24942 ,  Y10T428/26 ,  Y10T428/265

摘要： The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

摘要翻译： 本发明提供了包括在硅衬底上形成的氮化镓材料层的半导体材料以及形成半导体材料的方法。 半导体材料包括在硅衬底和氮化镓材料层之间形成的过渡层。 过渡层由氮化镓材料与衬底之间的热膨胀速率差异导致的氮化镓材料层中的应力成分梯度降低。 氮化镓材料层中的应力降低降低了形成裂纹的倾向。 因此，本发明能够生产包括几乎没有或没有裂纹的氮化镓材料层的半导体材料。 半导体材料可以用于许多微电子和光学应用中。

公开(公告)号：US20160197076A1

公开(公告)日：2016-07-07

申请号：US15066880

申请日：2016-03-10

申请人： KABUSHIKA KAISHA TOSHIBA

发明人： Yoshiki KAMATA

IPC分类号： H01L27/092 ,  H01L29/16 ,  H01L29/04 ,  H01L29/24 ,  H01L29/165 ,  H01L29/22 ,  H01L29/225 ,  H01L29/20 ,  H01L29/205

CPC分类号： H01L27/0924 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/04 ,  H01L29/1604 ,  H01L29/165 ,  H01L29/2003 ,  H01L29/2006 ,  H01L29/205 ,  H01L29/2206 ,  H01L29/225 ,  H01L29/247 ,  H01L29/786

摘要： According to one embodiment, a field-effect transistor includes a source region of a first conductivity type, a drain region of the first conductivity type and a channel region of the first conductivity type between the source region and the drain region, the source region, the drain region and the channel region being disposed in a polycrystalline semiconductor layer; a first layer including an amorphous semiconductor layer disposed on the channel region; a gate insulating layer disposed on the first layer; and a gate electrode disposed on the gate insulating layer.

摘要翻译： 根据一个实施例，场效应晶体管包括第一导电类型的源极区域，第一导电类型的漏极区域和源极区域和漏极区域之间的第一导电类型的沟道区域，源极区域， 漏极区域和沟道区域设置在多晶半导体层中; 包括设置在所述沟道区上的非晶半导体层的第一层; 设置在所述第一层上的栅极绝缘层; 以及设置在栅极绝缘层上的栅电极。

公开(公告)号：US09337037B2

公开(公告)日：2016-05-10

申请号：US14356960

申请日：2012-10-31

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Abdenacer Ait-Mani ,  Stephanie Huet

IPC分类号： H01L21/02 ,  H01L25/00 ,  H01L31/0232 ,  H01L21/18 ,  H01L21/683 ,  H01L21/304 ,  H01L29/205 ,  H01L29/225 ,  H01L27/146 ,  H01L31/0203 ,  G02B13/00

CPC分类号： H01L21/187 ,  G02B13/0085 ,  H01L21/02002 ,  H01L21/304 ,  H01L21/6835 ,  H01L25/00 ,  H01L27/14618 ,  H01L29/205 ,  H01L29/225 ,  H01L31/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for obtaining a heterogeneous substrate intended for use in the production of a semiconductor comprises the following steps: (a) obtaining a first substrate (2) made from a type II-VI or type III-V material and a second substrate (1), each substrate being substantially planar and each substrate having a pre-determined surface area; (b) grinding a non-through recess (10) into the second substrate (1), the surface area of said recess being greater than the surface area of the first substrate, such that the first substrate can be housed in the recess; (c) depositing a bonding material (15) in the recess (10); (d) depositing the first substrate (2) in the recess (10) of the second substrate and securing the first substrate in the second substrate at a temperature below 300° C.; and (e) leveling the first and second substrates in order to obtain a heterogeneous substrate having a substantially planar face (30).

摘要翻译： 用于获得用于制造半导体的非均相衬底的方法包括以下步骤：（a）获得由II-VI型或III-V族材料制成的第一衬底（2）和第二衬底（1） ），每个衬底基本上是平面的，并且每个衬底具有预定的表面积; （b）将非贯通凹部（10）研磨到所述第二基板（1）中，所述凹部的表面积大于所述第一基板的表面积，使得所述第一基板可容纳在所述凹部中; （c）在所述凹部（10）中沉积接合材​​料（15）; （d）将第一衬底（2）沉积在第二衬底的凹部（10）中，并将第一衬底固定在第二衬底中，温度低于300℃; 和（e）使第一和第二基板平整，以获得具有基本平坦的面（30）的异质基底。

公开(公告)号：US09235811B2

公开(公告)日：2016-01-12

申请号：US14205541

申请日：2014-03-12

申请人： Raytheon Company

发明人： Steven M. Stoltz

IPC分类号： H01L29/225 ,  G06N99/00 ,  H01L39/02 ,  H01L39/12 ,  H01L39/22 ,  H01L39/24 ,  H01L27/18

CPC分类号： G06N99/002 ,  H01L27/18 ,  H01L39/223

摘要： Embodiments are directed to engineering a structure, comprising: measuring energy eigenstates of a Hamiltonian, predicting a time evolution of a combination of two energy eigenstates based on the measurement, and creating an entangled quantum state for two coefficients of the two energy eigenstates such that an associated wavefunction is encouraged to undergo the predicted time evolution.

摘要翻译： 实施例涉及工程化结构，其包括：测量哈密尔顿算子的能量本征态，基于测量预测两个能量本征态的组合的时间演化，以及为两个能量本征态的两个系数创建纠缠量子态，使得 鼓励相关波函数经历预测时间演化。

公开(公告)号：US20150028288A1

公开(公告)日：2015-01-29

申请号：US14446313

申请日：2014-07-29

申请人： US Nano LLC

发明人： Anthony C. Onicha ,  Louise E. Sinks ,  Stefanie L. Weber

IPC分类号： H01L21/02 ,  H01L29/225 ,  H01L29/06

CPC分类号： H01L21/02603 ,  H01L21/02477 ,  H01L21/02513 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/02628

摘要： The present disclosure provides systems, processes, articles of manufacture, and compositions that relate to core/shell semiconductor nanowires. Specifically, the disclosure provides a novel semiconductor material, CdSe/ZnS core/shell nanowires, as well as a method of preparation thereof. The disclosure also provides a new continuous flow method of preparing core/shell nanowires, including CdSe/CdS core/shell nanowire and CdSe/ZnS core/shell nanowires.

摘要翻译： 本公开提供涉及核/壳半导体纳米线的系统，方法，制品和组合物。 具体地说，本发明提供新型的半导体材料CdSe / ZnS核/壳纳米线，以及其制备方法。 本发明还提供了一种制备核/壳纳米线的新型连续流动方法，包括CdSe / CdS核/壳纳米线和CdSe / ZnS核/壳纳米线。

公开(公告)号：US08928035B2

公开(公告)日：2015-01-06

申请号：US14084429

申请日：2013-11-19

申请人： International Rectifier Corporation

发明人： T. Warren Weeks, Jr. ,  Edwin L. Piner ,  Thomas Gehrke ,  Kevin J. Linthicum

IPC分类号： H01L29/66 ,  H01L29/15 ,  C30B23/02 ,  C30B25/02 ,  C30B25/18 ,  C30B29/40 ,  H01L21/02 ,  H01L33/00 ,  H01L33/32 ,  H01L29/205 ,  H01L29/225 ,  H01L29/20

CPC分类号： H01L29/155 ,  C30B23/02 ,  C30B23/025 ,  C30B25/02 ,  C30B25/18 ,  C30B25/183 ,  C30B29/06 ,  C30B29/403 ,  C30B29/406 ,  C30B29/68 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/02598 ,  H01L21/0262 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/225 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/78 ,  H01L33/0066 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/04 ,  H01L33/06 ,  H01L33/12 ,  H01L33/32 ,  Y10T428/24942 ,  Y10T428/26 ,  Y10T428/265

摘要： The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

摘要翻译： 本发明提供了包括在硅衬底上形成的氮化镓材料层的半导体材料以及形成半导体材料的方法。 半导体材料包括在硅衬底和氮化镓材料层之间形成的过渡层。 过渡层由氮化镓材料与衬底之间的热膨胀率差异导致的氮化镓材料层中的应力变得较低。 氮化镓材料层中的应力降低降低了形成裂纹的倾向。 因此，本发明能够生产包括几乎没有或没有裂纹的氮化镓材料层的半导体材料。 半导体材料可以用于许多微电子和光学应用中。