公开(公告)号：US08236702B2

公开(公告)日：2012-08-07

申请号：US12042340

申请日：2008-03-05

申请人： Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin ,  Po-Chao Tsao

发明人： Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin ,  Po-Chao Tsao

IPC分类号： H01L21/302

CPC分类号： H01L21/76802 ,  H01L21/76831 ,  H01L21/76897

摘要： A semiconductor substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer and the etching stop layer is then patterned to form a plurality of openings exposing the semiconductor substrate. A dielectric thin film is subsequently formed to cover the dielectric layer, the sidewalls of the openings, and the semiconductor substrate. The dielectric thin film disposed on the dielectric layer and the semiconductor substrate is then removed while the dielectric thin film disposed on the sidewalls remains.

摘要翻译： 提供具有蚀刻停止层和至少从底部到顶部设置的电介质层的半导体衬底。 然后对电介质层和蚀刻停止层进行图案化以形成暴露半导体衬底的多个开口。 随后形成介电薄膜以覆盖电介质层，开口的侧壁和半导体衬底。 然后去除设置在电介质层和半导体衬底上的电介质薄膜，同时保留设置在侧壁上的电介质薄膜。

公开(公告)号：US20120184105A1

公开(公告)日：2012-07-19

申请号：US13431945

申请日：2012-03-27

申请人： Pei-Yu Chou ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Jiunn-Hsiung Liao

IPC分类号： H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338

摘要： A method for forming openings is provided. First, a substrate with a silicon-containing photo resist layer thereon is provided. Second, a first photo resist pattern is formed on the silicon-containing photo resist layer. Later, a first etching procedure is carried out on the silicon-containing photo resist layer to form a plurality of first openings by using the first photo resist pattern as an etching mask. Next, a second photo resist pattern is formed on the silicon-containing photo resist layer. Then, a second etching procedure is carried out on the silicon-containing photo resist layer to form a plurality of second openings by using the second photo resist pattern as an etching mask.

摘要翻译： 提供一种形成开口的方法。 首先，提供其上具有含硅光刻胶层的基板。 其次，在含硅光致抗蚀剂层上形成第一光刻胶图案。 然后，通过使用第一光致抗蚀剂图案作为蚀刻掩模，在含硅光致抗蚀剂层上进行第一蚀刻步骤以形成多个第一开口。 接下来，在含硅光致抗蚀剂层上形成第二光致抗蚀剂图案。 然后，通过使用第二光致抗蚀剂图案作为蚀刻掩模，在含硅光致抗蚀剂层上进行第二蚀刻步骤以形成多个第二开口。

公开(公告)号：US20110294075A1

公开(公告)日：2011-12-01

申请号：US12786794

申请日：2010-05-25

申请人： Shin-Chi Chen ,  Jiunn-Hsiung Liao

发明人： Shin-Chi Chen ,  Jiunn-Hsiung Liao

IPC分类号： G03F7/20

CPC分类号： H01L21/0337

摘要： A patterning method of the present invention is described as follows. A mask layer and a patterned photoresist layer are formed on a target layer in sequence, wherein an etching rate of the mask layer is different from an etching rate of the target layer. A plurality of spacers is formed on sidewalls of the patterned photoresist layer respectively, wherein an etching rate of the spacers is different from the etching rate of the mask layer. The patterned photoresist layer is removed to form an opening between any two adjacent spacers. A portion of the mask layer is removed by using the spacers as a mask so as to form a patterned mask layer. A portion of the target layer is removed by using the patterned mask layer as a mask.

摘要翻译： 本发明的图案形成方法如下所述。 掩模层和图案化的光致抗蚀剂层依次形成在目标层上，其中掩模层的蚀刻速率与目标层的蚀刻速率不同。 分别在图案化的光致抗蚀剂层的侧壁上形成多个间隔物，其中间隔物的蚀刻速率与掩模层的蚀刻速率不同。 去除图案化的光致抗蚀剂层以形成任何两个相邻间隔物之间​​的开口。 通过使用间隔物作为掩模去除掩模层的一部分，以形成图案化掩模层。 通过使用图案化掩模层作为掩模来去除目标层的一部分。

公开(公告)号：US20110223768A1

公开(公告)日：2011-09-15

申请号：US12720671

申请日：2010-03-10

申请人： Ying-Chih LIN ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Feng-Yi Chang ,  Chih-Wen Feng ,  Shang-Yuan Tsai

发明人： Ying-Chih LIN ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Feng-Yi Chang ,  Chih-Wen Feng ,  Shang-Yuan Tsai

IPC分类号： H01L21/311

CPC分类号： H01L21/31116 ,  H01L21/02063 ,  H01L21/76802 ,  H01L21/76814

摘要： A method for forming contact openings is provided. First, a semiconductor device is formed on a substrate. Next, an etching stop layer, a first dielectric layer and a patterned photoresist layer are sequentially formed on the substrate. Next a portion of the first dielectric layer and a portion of the etching stop layer are removed to form an opening, wherein the portion of the first dielectric layer and the portion of the etching stop layer are not covered by the patterned photoresist layer. Next, the patterned photoresist layer is removed. Next, an over etching process is performed to remove the etching stop layer at a bottom of the opening and expose the semiconductor device in a nitrogen-free environment. The reactant gas of the over etching process includes fluorine-containing hydrocarbons, hydrogen gas and argon gas.

摘要翻译： 提供了形成接触开口的方法。 首先，在基板上形成半导体装置。 接下来，在衬底上依次形成蚀刻停止层，第一电介质层和图案化光致抗蚀剂层。 接下来，去除第一电介质层的一部分和蚀刻停止层的一部分以形成开口，其中第一介电层的一部分和蚀刻停止层的部分不被图案化的光致抗蚀剂层覆盖。 接下来，去除图案化的光致抗蚀剂层。 接下来，进行过蚀刻处理以去除开口底部的蚀刻停止层，并在无氮环境中暴露半导体器件。 过蚀刻工艺的反应气体包括含氟烃，氢气和氩气。

公开(公告)号：US20110076814A1

公开(公告)日：2011-03-31

申请号：US12959393

申请日：2010-12-03

申请人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L29/7843

摘要： First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on the first transistor, the second transistor and the isolation structure. A first etching process is performed by using a patterned photoresist disposed on the first active region as a mask to remove the second etching stop layer and a portion of the stress layer from the second active region. The patterned photoresist is removed, and a second etching process is performed by using the second etching stop layer of the first active region as a mask to remove the remaining stress layer and a portion of the first etching stop layer from the second active region.

摘要翻译： 首先，提供具有第一有源区和第二有源区的半导体基板。 第一有源区包括第一晶体管，第二有源区包括第二晶体管。 第一蚀刻停止层，应力层和第二蚀刻停止层设置在第一晶体管，第二晶体管和隔离结构上。 通过使用设置在第一有源区上的图案化光致抗蚀剂作为掩模来执行第一蚀刻工艺，以从第二有源区移除第二蚀刻停止层和应力层的一部分。 去除图案化的光致抗蚀剂，并且通过使用第一有源区的第二蚀刻停止层作为掩模来执行第二蚀刻工艺，以从第二有源区去除剩余的应力层和第一蚀刻停止层的一部分。

公开(公告)号：US20110068408A1

公开(公告)日：2011-03-24

申请号：US12959399

申请日：2010-12-03

申请人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L29/7843

摘要： A strained-silicon CMOS transistor includes: a semiconductor substrate having a first active region, a second active region, and an isolation structure disposed between the first active region and the second active region; a first transistor, disposed on the first active region; a second transistor, disposed on the second active region; a first etching stop layer, disposed on the first transistor and the second transistor; a first stress layer, disposed on the first transistor; a second etching stop layer, disposed on the first transistor and the first stress layer, wherein an edge of the first stress layer is aligned with that of the second etching stop layer; a second stress layer, disposed on the second transistor; and a third etching stop layer disposed on the second transistor and the second stress layer, wherein an edge of the second stress layer is aligned with that of the third etching stop layer.

摘要翻译： 应变硅CMOS晶体管包括：具有第一有源区，第二有源区和设置在第一有源区和第二有源区之间的隔离结构的半导体衬底; 第一晶体管，设置在第一有源区上; 第二晶体管，设置在第二有源区上; 第一蚀刻停止层，设置在第一晶体管和第二晶体管上; 第一应力层，设置在所述第一晶体管上; 第二蚀刻停止层，设置在第一晶体管和第一应力层上，其中第一应力层的边缘与第二蚀刻停止层的边缘对准; 第二应力层，设置在所述第二晶体管上; 以及设置在所述第二晶体管和所述第二应力层上的第三蚀刻停止层，其中所述第二应力层的边缘与所述第三蚀刻停止层的边缘对准。

公开(公告)号：US07592265B2

公开(公告)日：2009-09-22

申请号：US11620028

申请日：2007-01-04

申请人： Meng-Jun Wang ,  Yi-Hsing Chen ,  Min-Chieh Yang ,  Jiunn-Hsiung Liao

发明人： Meng-Jun Wang ,  Yi-Hsing Chen ,  Min-Chieh Yang ,  Jiunn-Hsiung Liao

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/28123 ,  H01L21/0271 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32139 ,  H01L21/7624 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/947 ,  Y10S438/95

摘要： A method of trimming hard mask is provided. The method includes providing a substrate, a hard mask layer, and a tri-layer stack on the substrate. The tri-layer stack includes a top photo resist layer, a silicon photo resist layer, and a bottom photo resist layer. The top photo resist layer, the silicon photo resist layer, the bottom photo resist layer, and the hard mask layer are patterned sequentially. A trimming process is performed on the hard mask layer. The bottom photo resist layer of the present invention is thinner and loses some height in the etching process, so the bottom photo resist layer will not collapse.

摘要翻译： 提供了修剪硬掩模的方法。 该方法包括在衬底上提供衬底，硬掩模层和三层堆叠。 三层堆叠包括顶部光致抗蚀剂层，硅光致抗蚀剂层和底部光致抗蚀剂层。 顺序地对顶部光致抗蚀剂层，硅光致抗蚀剂层，底部光致抗蚀剂层和硬掩模层进行图案化。 在硬掩模层上进行修整处理。 本发明的底部光致抗蚀剂层在蚀刻工艺中更薄并且损失一些高度，因此底部光致抗蚀剂层将不会塌陷。

公开(公告)号：US20090206403A1

公开(公告)日：2009-08-20

申请号：US12430107

申请日：2009-04-27

申请人： Meng-Jun Wang ,  Yi-Hsing Chen ,  Min-Chieh Yang ,  Jiunn-Hsiung Liao

发明人： Meng-Jun Wang ,  Yi-Hsing Chen ,  Min-Chieh Yang ,  Jiunn-Hsiung Liao

IPC分类号： H01L29/06

CPC分类号： H01L21/28123 ,  H01L21/0271 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32139 ,  H01L21/7624 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/947 ,  Y10S438/95

摘要： A stack structure for forming a gate of a MOS transistor includes a substrate including a plurality of shallow trench isolations therein; a dielectric layer, a conductive layer and a hard mask layer formed on the substrate in sequence; and a tri-layer stack comprising a top photo resist layer, a silicon-containing photo resist layer and a bottom anti-reflective coating (BARC) on the hard mask layer, wherein the silicon-containing photo resist layer comprises 10-30% silicon and the hard mask layer has a high etching selectivity ratio to the conductive layer.

摘要翻译： 用于形成MOS晶体管的栅极的堆叠结构包括其中包括多个浅沟槽隔离的衬底; 依次形成在基板上的电介质层，导电层和硬掩模层; 以及包括在所述硬掩模层上的顶部光致抗蚀剂层，含硅光刻胶层和底部抗反射涂层（BARC）的三层堆叠，其中所述含硅光致抗蚀剂层包括10-30％的硅 并且硬掩模层与导电层具有高蚀刻选择性比。

公开(公告)号：US20090145877A1

公开(公告)日：2009-06-11

申请号：US12371809

申请日：2009-02-16

申请人： Feng-Yih Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

发明人： Feng-Yih Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

IPC分类号： B44C1/22

CPC分类号： H01L21/76804 ,  H01L21/31144 ,  H01L21/76895

摘要： A method for controlling an ADI-AEI CD difference ratio of openings having different sizes is described. The openings are formed through a silicon-containing material layer, an etching resistive layer and a target material layer in turn. Before the opening etching steps, at least one of the opening patterns in the photoresist mask is altered in size through photoresist trimming or deposition of a substantially conformal polymer layer. A first etching step forming thicker polymer on the sidewall of the wider opening pattern is performed to form a patterned Si-containing material layer. A second etching step is performed to remove exposed portions of the etching resistive layer and the target material layer. At least one parameter among the parameters of the photoresist trimming or polymer layer deposition step and the etching parameters of the first etching step is controlled to obtain a predetermined ADI-AEI CD difference ratio.

摘要翻译： 描述了用于控制具有不同尺寸的开口的ADI-AEI CD差异比率的方法。 开口依次形成为含硅材料层，蚀刻电阻层和靶材料层。 在开口蚀刻步骤之前，光致抗蚀剂掩模中的至少一个开口图案的尺寸通过基本上保形的聚合物层的光致抗蚀剂修饰或沉积而改变。 执行在更宽的开口图案的侧壁上形成较厚聚合物的第一蚀刻步骤以形成图案化的含Si材料层。 执行第二蚀刻步骤以去除蚀刻电阻层和目标材料层的暴露部分。 控制光致抗蚀剂修整或聚合物层沉积步骤的参数中的至少一个参数和第一蚀刻步骤的蚀刻参数以获得预定的ADI-AEI CD差异比。

公开(公告)号：US20090142931A1

公开(公告)日：2009-06-04

申请号：US11946875

申请日：2007-11-29

申请人： Chieh-Ju Wang ,  Jyh-Cherng Yau ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

发明人： Chieh-Ju Wang ,  Jyh-Cherng Yau ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC分类号： H01L21/461 ,  C23F1/12

CPC分类号： H01L21/02063 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76814

摘要： A cleaning method following an opening etching is provided. First, a semiconductor substrate having a dielectric layer is provided. The hard mask layer includes at least a metal layer. The opening etch is then carried out to form at least an opening in the dielectric layer. A nitrogen (N2) treatment process is performed to clean polymer residues having carbon-fluorine (C—F) bonds remained in the opening. Finally, a wet cleaning process is performed.

摘要翻译： 提供了开口蚀刻后的清洁方法。 首先，提供具有电介质层的半导体基板。 硬掩模层至少包括金属层。 然后进行开口蚀刻以形成电介质层中的至少一个开口。 进行氮（N2）处理工艺以清洁残留在开口中的具有碳 - 氟（C-F）键的聚合物残基。 最后，进行湿式清洗处理。