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115 条记录 (耗时 0.025 秒)

    Radical oxidation process for fabricating a nonvolatile charge trap memory device
    21.
    发明授权
    Radical oxidation process for fabricating a nonvolatile charge trap memory device 有权
    用于制造非易失性电荷陷阱存储器件的自由基氧化工艺

    公开(公告)号：US08940645B2

    公开(公告)日：2015-01-27

    申请号：US13539458

    申请日：2012-07-01

    申请人： Krishnaswamy Ramkumar ,  Sagy Levy ,  Jeong Byun

    发明人： Krishnaswamy Ramkumar ,  Sagy Levy ,  Jeong Byun

    IPC分类号： H01L21/31

    CPC分类号： H01L29/7926 ,  B82Y10/00 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02271 ,  H01L21/02326 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28282 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/775

    摘要： A method for fabricating a nonvolatile charge trap memory device is described. The method includes subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a polysilicon channel, and forming over the tunnel oxide layer a multi-layer charge storing layer comprising an oxygen-rich, first layer comprising a nitride, and an oxygen-lean, second layer comprising a nitride on the first layer. The substrate is then subjected to a second oxidation process to consume a portion of the second layer and form a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The stoichiometric composition of the first layer results in it being substantially trap free, and the stoichiometric composition of the second layer results in it being trap dense. The second oxidation process can comprise a plasma oxidation process or a radical oxidation process using In-Situ Steam Generation.

    摘要翻译： 描述了制造非易失性电荷陷阱存储器件的方法。 所述方法包括使衬底经受第一氧化工艺以形成覆盖多晶硅沟道的隧道氧化物层，以及在所述隧道氧化物层上形成多层电荷存储层，所述多层电荷存储层包含富氧的第一层，所述第一层包含氮化物，以及 在第一层上包含氮化物的贫氧第二层。 然后对衬底进行第二氧化处理以消耗第二层的一部分并形成覆盖多层电荷存储层的高温氧化物（HTO）层。 第一层的化学计量组成导致其基本上无陷阱，并且第二层的化学计量组成使其陷入致密。 第二氧化过程可以包括使用原位蒸汽发生的等离子体氧化过程或自由基氧化过程。

    Memory transistor with multiple charge storing layers and a high work function gate electrode
    22.
    发明授权
    Memory transistor with multiple charge storing layers and a high work function gate electrode 有权
    具有多个电荷存储层和高功函数栅电极的存储晶体管

    公开(公告)号：US08859374B1

    公开(公告)日：2014-10-14

    申请号：US13288919

    申请日：2011-11-03

    申请人： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

    发明人： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

    IPC分类号： H01L21/336

    CPC分类号： H01L29/513 ,  G11C16/0466 ,  G11C16/349 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/28035 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

    摘要： Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the method comprises: (i) forming an oxide-nitride-oxide (ONO) dielectric stack on a surface of a semiconductor substrate in at least a first region in which a non-volatile memory transistor is to be formed, the ONO dielectric stack including a multi-layer charge storage layer; (ii) forming an oxide layer on the surface of the substrate in a second region in which a metal oxide semiconductor (MOS) logic transistor is to be formed; and (iii) forming a high work function gate electrode on a surface of the ONO dielectric stack. Other embodiments are also disclosed.

    摘要翻译： 提供包括非易失性存储晶体管的半导体器件及其制造方法以改善其性能。 在一个实施例中，该方法包括：（i）在其中将形成非易失性存储晶体管的至少第一区域中，在半导体衬底的表面上形成氧化物 - 氧化物 - 氧化物（ONO）电介质叠层， ONO电介质堆叠包括多层电荷存储层; （ii）在要形成金属氧化物半导体（MOS）逻辑晶体管的第二区域中在所述衬底的表面上形成氧化物层; 和（iii）在ONO电介质叠层的表面上形成高功函数栅电极。 还公开了其他实施例。

    Integration of non-volatile charge trap memory devices and logic CMOS devices
    23.
    发明授权
    Integration of non-volatile charge trap memory devices and logic CMOS devices 有权
    集成非易失性电荷陷阱存储器件和逻辑CMOS器件

    公开(公告)号：US08679927B2

    公开(公告)日：2014-03-25

    申请号：US12185751

    申请日：2008-08-04

    申请人： Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy

    发明人： Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy

    IPC分类号： H01L29/792

    CPC分类号： H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7836 ,  H01L29/7843

    摘要： A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

    摘要翻译： 一种半导体结构及其形成方法。 半导体结构包括具有设置在第一区域上的非易失性电荷陷阱存储器件和设置在第二区域上的逻辑器件的衬底。 可以在形成逻辑器件的阱和通道之后形成电荷陷阱电介质叠层。 可以避免HF预清洗和SC1清洁，以提高非挥发性电荷陷阱存储器件的阻挡层的质量。 在逻辑MOS栅极绝缘体层的热氧化或氮化期间，阻挡层可以被热再氧化或氮化，以致密封阻挡层。 可以使用多层衬垫来首先在高压逻辑器件中偏置源极和漏极注入，并且还阻挡非易失性电荷陷阱存储器件的硅化。

    Sequential deposition and anneal of a dielectic layer in a charge trapping memory device
    25.
    发明授权
    Sequential deposition and anneal of a dielectic layer in a charge trapping memory device 有权
    在电荷俘获存储器件中的介电层的顺序沉积和退火

    公开(公告)号：US08088683B2

    公开(公告)日：2012-01-03

    申请号：US12080166

    申请日：2008-03-31

    申请人： Krishnaswamy Ramkumar ,  Sagy Levy

    发明人： Krishnaswamy Ramkumar ,  Sagy Levy

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/28282 ,  H01L21/3145

    摘要： Deposition and anneal operations are iterated to break a deposition into a number of sequential deposition-anneal operations to reach a desired annealed dielectric layer thickness. In one particular embodiment, a two step anneal is performed including an NH3 or ND3 ambient followed by an N2O or NO ambient. In one embodiment, such a method is employed to form a dielectric layer having a stoichiometry attainable with only a deposition process but with a uniform material quality uncharacteristically high of a deposition process. In particular embodiments, sequential deposition-anneal operations provide an annealed first dielectric layer upon which a second dielectric layer may be left substantially non-annealed.

    摘要翻译： 重复沉积和退火操作以将沉积破坏成多个顺序的沉积退火操作以达到期望的退火介电层厚度。 在一个具体实施方案中，进行包括NH 3或ND 3环境，随后是N 2 O或NO环境的两步退火。 在一个实施例中，采用这种方法形成具有仅通过沉积工艺可获得的化学计量但具有均匀材料质量的电介质层，这在沉积过程中具有非常高的特性。 在特定实施例中，顺序沉积 - 退火操作提供退火的第一介电层，第二介电层可以在其上基本上保持不退火。

    Methods for fabricating semiconductor memory with process induced strain
    28.
    发明授权
    Methods for fabricating semiconductor memory with process induced strain 有权
    用工艺诱导应变制造半导体存储器的方法

    公开(公告)号：US08691648B1

    公开(公告)日：2014-04-08

    申请号：US13168711

    申请日：2011-06-24

    申请人： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar ,  Jeong Soo Byun

    发明人： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar ,  Jeong Soo Byun

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28282 ,  H01L29/66833 ,  H01L29/792

    摘要： Non-volatile semiconductor memories and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the method includes: (i) forming a gate for a non-volatile memory transistor on a surface of a substrate overlaying a channel region formed therein, the gate including a charge trapping layer; and (ii) forming a strain inducing structure over the gate of the non-volatile memory transistor to increase charge retention of the charge trapping layer. Preferably, the memory transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) transistor comprising a SONOS gate stack. More preferably, the memory also includes a logic transistor on the substrate, and the step of forming a strain inducing structure comprises the step of forming the strain inducing structure over the logic transistor. Other embodiments are also disclosed.

    摘要翻译： 提供非易失性半导体存储器及其制造方法以改善其性能。 在一个实施例中，该方法包括：（i）在覆盖其中形成的沟道区的衬底的表面上形成用于非易失性存储晶体管的栅极，栅极包括电荷俘获层; 和（ii）在非易失性存储晶体管的栅极上形成应变诱导结构，以增加电荷俘获层的电荷保留。 优选地，存储晶体管是包括SONOS栅极堆叠的氧化硅 - 氧化物 - 氮化物 - 氧化物 - 硅（SONOS）晶体管。 更优选地，存储器还包括在衬底上的逻辑晶体管，并且形成应变诱导结构的步骤包括在逻辑晶体管上形成应变诱导结构的步骤。 还公开了其他实施例。

    Nitridation oxidation of tunneling layer for improved SONOS speed and retention
    30.
    发明授权
    Nitridation oxidation of tunneling layer for improved SONOS speed and retention 有权
    隧道层的氮化氧化提高了SONOS的速度和保留时间

    公开(公告)号：US08637921B2

    公开(公告)日：2014-01-28

    申请号：US12005813

    申请日：2007-12-27

    申请人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne

    发明人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne

    IPC分类号： H01L29/792

    CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L21/3143 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518

    摘要： A method for forming a tunneling layer of a nonvolatile trapped-charge memory device and the article made thereby. The method includes multiple oxidation and nitridation operations to provide a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. The method provides for an improved memory window in a SONOS-type device. In one embodiment, the method includes an oxidation, a nitridation, a reoxidation and a renitridation. In one implementation, the first oxidation is performed with O2 and the reoxidation is performed with NO.

    摘要翻译： 一种用于形成非易失性俘获电荷存储装置的隧道层的方法及其制成的制品。 该方法包括多次氧化和氮化操作，以提供比纯二氧化硅隧道层更高的介电常数，但是具有比在衬底界面处具有氮的隧穿层更少的氢和氮阱。 该方法提供了SONOS型设备中改进的存储器窗口。 在一个实施方案中，所述方法包括氧化，氮化，再氧化和再纳入。 在一个实施方案中，首先用O 2进行氧化，并用NO进行再氧化。