公开(公告)号：US06510185B2

公开(公告)日：2003-01-21

申请号：US09897975

申请日：2001-07-05

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： H03D324

CPC分类号： H03H11/22 ,  H03D7/1441 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/403

摘要： A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention includes an antenna for receiving transmitting RF signals, a PLL for generating multi-phase clock signals having a frequency different from a carrier frequency in response to the multi-phase clock signals and a reference signal having the carrier frequency, a demodulation-mixing unit for mixing the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output the RF signals having a frequency reduced by the carrier frequency and an A/D converting unit for converting the RF signals from the mixing unit into digital signals.

公开(公告)号：US06424192B1

公开(公告)日：2002-07-23

申请号：US09709311

申请日：2000-11-13

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： H03L706

CPC分类号： H04B1/403 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/0996 ,  H03L7/1974 ,  H04B1/28 ,  H04B1/40

摘要： A phase lock loop (PLL) and methods for using same is provided that includes a multiple-feedback CMOS voltage control oscillator (VCO) and multi-phase sampling fractional-N prescaler. The PLL provides increased performance characteristics for a single chip CMOS radio frequency (RF) communications system. The multiple feedback CMOS VCO maintains an amplitude of a VCO signal while reducing a rise/fall time of the VCO signal. The multiple feedback CMOS VCO further reduces supply noise effects. The multi-phase sampling fractional-N prescaler provides sufficient bandwidth for a CMOS VCO while maintaining spectral purity and reducing fractional-spur. The multi-phase sampling fractional-N prescaler can include a divider, a sampler circuit, a selector circuit and a modular counter.

公开(公告)号：US06404277B1

公开(公告)日：2002-06-11

申请号：US09709310

申请日：2000-11-13

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： H03K501

CPC分类号： H04B1/28 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/40 ,  H04B1/403

摘要： A tuning circuit for an RF communications system and method includes a master block that outputs a control signal to a slave block. The master block can include a first filter having a high pass filter and a low pass filter that each receive the control signal, a first rectifier coupled to the high pass filter, a second rectifier coupled to the low pass filter, and a converter coupled to the first and second rectifiers that outputs the control signal. The first filter is preferably a gm-C poly-phase filter. Output signals of the gm-C poly-phase filter include high and low pass filtering signals resulting from similarly configured circuits so that the output signals have the same electrical characteristics, which results in an increased accuracy, for example, in a cut-off frequency.

公开(公告)号：US08289314B2

公开(公告)日：2012-10-16

申请号：US12569186

申请日：2009-09-29

申请人： Weon-Jun Choe ,  Ah-Reum Kim ,  Kyo-Jin Choo ,  Deog-Kyoon Jeong ,  Do-Hwan Oh ,  Hee-Soo Song

发明人： Weon-Jun Choe ,  Ah-Reum Kim ,  Kyo-Jin Choo ,  Deog-Kyoon Jeong ,  Do-Hwan Oh ,  Hee-Soo Song

IPC分类号： G06F3/038 ,  G11B7/00

CPC分类号： G09G3/20 ,  G09G3/3648 ,  G09G2310/08 ,  G09G2370/08 ,  H03K7/04

摘要： A method of modulating and demodulating a signal includes modulating data information included in an input data signal provided from an external source and clock information included in an input clock signal provided from the external source into a transmission signal, using (n+1) delay clock signals generated based on the input clock signal, where n is a natural number. The transmission signal is demodulated into an output clock signal including restored clock information and an output data signal including restored data information, using (m+1) delay clock signals generated based on the clock information, where m is a natural number less than n.

摘要翻译： 调制和解调信号的方法包括：使用（n + 1）个延迟时钟将从外部源提供的输入数据信号中包括的数据信息和从外部源提供的输入时钟信号中包括的时钟信息调制成发送信号 基于输入时钟信号生成的信号，其中n是自然数。 使用基于时钟信息生成的（m + 1）个延迟时钟信号，将发送信号解调为包括恢复的时钟信息的输出时钟信号和包括恢复的数据信息的输出数据信号，其中m是小于n的自然数。

公开(公告)号：US20120206176A1

公开(公告)日：2012-08-16

申请号：US13398245

申请日：2012-02-16

申请人： Moon-Sang Hwang ,  Won-Jun Choe ,  Han-Kyu Chi ,  Deog-Kyoon Jeong

发明人： Moon-Sang Hwang ,  Won-Jun Choe ,  Han-Kyu Chi ,  Deog-Kyoon Jeong

IPC分类号： H03L7/08

CPC分类号： H03L7/0812 ,  H03L7/095 ,  H03L7/101

摘要： A coarse lock detector is disclosed. The course lock detector uses an initial lock range to determine course lock, and once course lock is achieved, uses a modified lock range to determine course lock.

摘要翻译： 公开了一种粗锁检测器。 课程锁定检测器使用初始锁定范围来确定课程锁定，并且一旦达到课程锁定，则使用修改的锁定范围来确定课程锁定。

公开(公告)号：US20090219739A1

公开(公告)日：2009-09-03

申请号：US12223552

申请日：2006-09-15

申请人： Young-Deok Kim ,  Deog-Kyoon Jeong

发明人： Young-Deok Kim ,  Deog-Kyoon Jeong

IPC分类号： G11C15/04 ,  G11C15/00

CPC分类号： G11C15/04

摘要： A range-matching cell (RMC) includes bit lines (BL); a word line (WL); a match line (ML); search lines (SL); a memory cell (100); a first comparator (110) connected to the memory cell; a second comparator (120) connected to the first comparator, a ground voltage and a predetermined voltage. The comparators conduct a comparing operation in responsive to operator data. Instead of the conventional TCAMs employing 0, 1, and X (don't care) bit, a CAM utilizing the RMC can conduct a comparing operation with less memory by storing the operator data 0 and 1 in advance. Accordingly, memory-use efficiency can be increased.

摘要翻译： 范围匹配单元（RMC）包括位线（BL）; 字线（WL）; 匹配线（ML）; 搜索行（SL）; 存储单元（100）; 连接到所述存储单元的第一比较器（110） 连接到第一比较器的第二比较器（120），接地电压和预定电压。 比较器根据操作员数据进行比较操作。 代替采用0，1和X（无关）位的常规TCAM，使用RMC的CAM可以通过预先存储操作数据0和1来进行具有较少存储器的比较操作。 因此，可以提高记忆使用效率。

公开(公告)号：US07113507B2

公开(公告)日：2006-09-26

申请号：US10053461

申请日：2001-11-07

申请人： Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

发明人： Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

IPC分类号： H04J3/12 ,  H04L12/56

CPC分类号： H04L47/10 ,  H04L47/245 ,  H04L47/34 ,  H04L47/365

摘要： A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

公开(公告)号：US07102446B1

公开(公告)日：2006-09-05

申请号：US11056995

申请日：2005-02-11

申请人： Hyung-Rok Lee ,  Moon-Sang Hwang ,  Sang-Hyun Lee ,  Bong-Joon Lee ,  Deog-Kyoon Jeong

发明人： Hyung-Rok Lee ,  Moon-Sang Hwang ,  Sang-Hyun Lee ,  Bong-Joon Lee ,  Deog-Kyoon Jeong

IPC分类号： H03L7/07 ,  H03L7/087 ,  H04B1/40 ,  H04B1/50

CPC分类号： H03L7/087 ,  H03K23/507 ,  H03L7/089 ,  H03L7/093 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/10 ,  H03L2207/06 ,  H04L7/0337 ,  Y10S331/02

摘要： A phase lock loop (PLL) for controlling a sampling clock or other clock, and a data sampling circuit, transceiver, or other device including such a PLL. The PLL includes a multi-range VCO, at least one fine control loop for controlling the VCO, and a coarse control loop for controlling the VCO by changing its frequency-voltage characteristic. The coarse control loop includes a frequency lock detector and voltage range monitoring logic. Typically, the frequency lock detector locks operation of the coarse control loop when the difference between the VCO output clock frequency and a reference frequency decreases to within a predetermined threshold, and the unlocked coarse control loop employs the voltage range monitoring logic to change the VCO frequency-voltage characteristic when the VCO's fine control voltage leaves a predetermined range. Other aspects are a transceiver (including at least two receiver interfaces and a transmitter interface) implementing a clocking scheme employing no more than three PLLs for clock generation, and a transceiver having a multi-layered receiver interface including digital circuitry and a single clock-generating PLL (an analog PLL for generating a multiphase clock to be shared by all layers of the receiver interface). Each receiver interface layer performs blind oversampling on a different received signal using the multiphase clock and the digital circuitry includes multilayered digital phase lock loop circuitry which receives the oversampled data.

摘要翻译： 用于控制采样时钟或其他时钟的锁相环（PLL）以及数据采样电路，收发器或包括这种PLL的其它装置。 PLL包括多范围VCO，用于控制VCO的至少一个精细控制环路和用于通过改变其频率 - 电压特性来控制VCO的粗略控制环路。 粗调控制回路包括一个频率锁定检测器和电压范围监控逻辑。 通常，当VCO输出时钟频率和参考频率之间的差减小到预定阈值时，频率锁定检测器锁定粗略控制环路的操作，而解锁的粗略控制环路采用电压范围监控逻辑来改变VCO频率 当VCO的精细控制电压离开预定范围时的电压特性。 其他方面是实现采用不超过三个PLL用于时钟产生的时钟方案的收发器（包括至少两个接收器接口和发射器接口），以及具有包括数字电路和单个时钟产生的多层接收器接口的收发器 PLL（用于产生要由接收器接口的所有层共享的多相时钟的模拟PLL）。 每个接收器接口层使用多相时钟在不同的接收信号上执行盲过采样，并且数字电路包括接收过采样数据的多层数字锁相环电路。

公开(公告)号：US06738417B1

公开(公告)日：2004-05-18

申请号：US09393849

申请日：1999-09-09

申请人： Sungjoon Kim ,  Deog-Kyoon Jeong ,  David D. Lee

发明人： Sungjoon Kim ,  Deog-Kyoon Jeong ,  David D. Lee

IPC分类号： H04B138

CPC分类号： H04L5/14 ,  G06F3/14 ,  G09G1/16 ,  G09G2370/045

摘要： A new scheme to transfer bidirectional data streams between a digital display and a computer is disclosed. This bidirectional data transfer can make several I/O devices attach to a display. Existing digital display interfaces are usually unidirectional from a computing to a display. Due to the nature of the existing clocking scheme, backward data transfer from the display side to the computer requires a backward clock. This invention discloses a scheme to send data bidirectionally without sending the additional backward clock. This invention also discloses a scheme to tolerate jitters from the clock source. With this approach, this new interface can make a digital display an I/O concentrator.

摘要翻译： 公开了一种在数字显示器和计算机之间传输双向数据流的新方案。 这种双向数据传输可以使多个I / O设备连接到显示器。 现有的数字显示接口通常是从计算到显示的单向的。 由于现有的时钟方案的性质，从显示侧到计算机的反向数据传输需要一个反向时钟。 本发明公开了一种双向发送数据的方案，而不发送额外的反向时钟。 本发明还公开了一种允许来自时钟源的抖动的方案。 通过这种方式，这个新界面可以使数字显示器成为一个I / O集中器。

公开(公告)号：US06271816B1

公开(公告)日：2001-08-07

申请号：US09148583

申请日：1998-09-04

申请人： Deog-Kyoon Jeong ,  Gyudong Kim

发明人： Deog-Kyoon Jeong ,  Gyudong Kim

IPC分类号： G09G336

CPC分类号： G09G3/3655 ,  G09G3/3614 ,  G09G3/3648 ,  G09G3/3688 ,  G09G2310/0248 ,  G09G2330/021 ,  G09G2330/023

摘要： Switches and capacitors are efficiently used to passively change the voltage level on column electrodes without active driving by the column driver circuit. This significantly reduces the power needed by the column driver circuit to drive voltages of alternating polarity onto the column electrodes. In this way, significant power is saved in both the pixel inversion and the row inversion schemes. The average power savings of various of the embodiments exceeds 50% compared with a simple conventional implementation of a column driver circuit. Another aspect similarly reduces the power used by the column driver circuit in the back plane switching scheme.

摘要翻译： 开关和电容器被有效地用于被动地改变列电极上的电压电平，而无需由列驱动电路进行有源驱动。 这显着地降低了列驱动电路所需的功率，以驱动交替极性的电压到列电极上。 以这种方式，在像素反转和行反转方案中节省了显着的功率。 与列驱动电路的简单常规实施方式相比，各种实施例的平均功率节省超过了50％。 另一方面类似地减少了在背面切换方案中列驱动电路所使用的功率。