公开(公告)号：US20190312050A1

公开(公告)日：2019-10-10

申请号：US15950021

申请日：2018-04-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI ,  Hsiang-Lan LUNG

IPC: H01L27/11582 ,  H01L23/535 ,  H01L23/528 ,  H01L29/66

Abstract: A memory device includes a stack of conductive strips in a plurality of first levels with a first opening and a conductive strip in the second level with a second opening, both openings exposing sidewalls. Data storage structures are formed on the sidewalls of the conductive strips in the plurality of first levels. A first vertical channel structure including vertical channel films is disposed in the first opening, the vertical channel films in contact with the data storage structures. The second opening is aligned with the first vertical channel structure. A gate dielectric layer is disposed on the sidewall of the conductive strip in the second level. A second vertical channel structure including vertical channel films is disposed in the second opening in contact with the gate dielectric layer on the sidewall of the conductive strip in the second level.

公开(公告)号：US20230284463A1

公开(公告)日：2023-09-07

申请号：US17686484

申请日：2022-03-04

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI ,  Hsiang-Lan LUNG ,  Chiao-Wen YEH

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1293 ,  H01L45/1675

Abstract: A memory structure and a manufacturing method for the same are provided. The memory structure includes a memory element, a spacer structure, and an upper element structure. The memory element includes a lower memory layer and an upper memory layer on the lower memory layer. The spacer structure is on a sidewall surface of the lower memory layer. The upper element structure is electrically connected on the upper memory layer. A recess is defined by a lower surface of the upper element structure, an upper surface of the lower memory layer and a sidewall surface of the upper memory layer.

公开(公告)号：US20220328686A1

公开(公告)日：2022-10-13

申请号：US17228795

申请日：2021-04-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11582

Abstract: A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure comprises a channel element. The channel element comprises a substrate portion and a vertical channel portion. The vertical channel portion is adjoined on the substrate portion. The substrate portion and the vertical channel portion both comprise single crystal silicon.

公开(公告)号：US20210249435A1

公开(公告)日：2021-08-12

申请号：US17004048

申请日：2020-08-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI

IPC: H01L27/11582 ,  H01L27/1157 ,  G11C7/18 ,  G11C8/14

Abstract: A memory device and a manufacturing for the same are provided. The memory device comprises a channel line, word lines, a first switch, and a second switch. Memory cells for a memory string are defined at intersections between the channel line and the word lines. The first switch is electrically connected with the channel line. The second switch is electrically connected with the channel line. The first switch is electrically connected between the second switch and the memory cells.

公开(公告)号：US20210242072A1

公开(公告)日：2021-08-05

申请号：US16782093

申请日：2020-02-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI ,  Hsiang-Lan LUNG

IPC: H01L21/764 ,  H01L27/11582 ,  H01L23/528 ,  H01L21/311 ,  H01L21/02 ,  H01L21/768 ,  H01L21/28

Abstract: A three-dimensional memory device includes a substrate, a plurality of horizontal conductive layers, a plurality of vertical memory structures and a vertical conductive post. The conductive layers are located above the substrate, and immediately-adjacent two of the conductive layers are spaced by a first air gap. The memory structures pass through the conductive layers and are connected to the substrate. The conductive post is located between immediately-adjacent two of the memory structures and passes through the conductive layers and is connected to the substrate. The conductive post is spaced from immediately-adjacent edges of the conductive layers by a second air gap.

公开(公告)号：US20210143216A1

公开(公告)日：2021-05-13

申请号：US17154615

申请日：2021-01-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI ,  Hsiang-Lan LUNG

IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

Abstract: A plurality of memory cells in a cross-point array in which the memory cell stacks in the cross-points include a switch element, a conductive barrier layer, and a confined cell structure in series, and having sides aligned within the cross-point area of the corresponding cross-point, the confined cell structure including surfactant spacers within the cross-point area having outside surfaces on a pair of opposing sides of the stack, and a body of programmable resistance memory material confined between inside surfaces of the surfactant spacers. The memory cells can be operated as multi-level cells in a 3D array.

公开(公告)号：US20190393268A1

公开(公告)日：2019-12-26

申请号：US16014346

申请日：2018-06-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI ,  Hsiang-Lan LUNG

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: A plurality of memory cells in a cross-point array in which the memory cell stacks in the cross-points include a switch element, a conductive barrier layer, and a confined cell structure in series, and having sides aligned within the cross-point area of the corresponding cross-point, the confined cell structure including surfactant spacers within the cross-point area having outside surfaces on a pair of opposing sides of the stack, and a body of programmable resistance memory material confined between inside surfaces of the surfactant spacers. The memory cells can be operated as multi-level cells in a 3D array.

公开(公告)号：US20190355790A1

公开(公告)日：2019-11-21

申请号：US16233524

申请日：2018-12-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hsiang-Lan LUNG ,  Erh-Kun LAI ,  Ming-Hsiu LEE ,  Chiao-Wen YEH

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00 ,  G11C8/14 ,  G11C7/18

Abstract: An integrated circuit includes a three-dimensional cross-point memory having a plurality of levels of memory cells disposed in cross points of first access lines and second access lines with alternating wide and narrow regions. The manufacturing process of the three-dimensional cross-point memory includes patterning with three patterns: a first pattern to define the memory cells, a second pattern to define the first access lines, and a third pattern to define the second access lines.

公开(公告)号：US20160260898A1

公开(公告)日：2016-09-08

申请号：US14638189

申请日：2015-03-04

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI ,  Feng-Min LEE ,  Yu-Yu LIN

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1253 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1625 ,  H01L45/1633

Abstract: A method is provided for manufacturing a memory. An insulating layer is formed over an array of interlayer conductors, and etched to define a first opening corresponding to a first interlayer conductor in the array, where the etching stops at a first top surface of the first interlayer conductor. A metal oxide layer is formed on the first top surface. A first layer of barrier material is deposited conformal with and contacting the metal oxide layer and surfaces of the first opening. Subsequently the insulating layer is etched to define a second opening corresponding to a second interlayer conductor in the array, where the etching stops at a second top surface of the second interlayer conductor. A second layer of barrier material is deposited conformal with and contacting the first layer of barrier material in the first opening. The first opening is filled with a conductive material.

Abstract translation: 提供了一种用于制造存储器的方法。 在层间导体阵列之上形成绝缘层，并蚀刻以形成对应于阵列中的第一层间导体的第一开口，其中蚀刻停止在第一层间导体的第一顶表面处。 金属氧化物层形成在第一顶表面上。 第一层阻挡材料与第一开口的金属氧化物层和表面共形并与其接触。 随后，绝缘层被蚀刻以限定对应于阵列中的第二层间导体的第二开口，其中蚀刻停止在第二层间导体的第二顶表面处。 第二层阻挡材料与第一开口中的第一阻隔材料层共形并与其接触。 第一个开口填充有导电材料。