公开(公告)号：US20240008249A1

公开(公告)日：2024-01-04

申请号：US18047662

申请日：2022-10-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen CHEN ,  Hang-Ting LUE

IPC: H01L27/108

CPC classification number: H01L27/10802

Abstract: A memory structure includes a substrate, a first gate structure, a second gate structure, a third gate structure, and channel bodies separated from each other and passing through the first gate structure, the second gate structure and the third gate structure along a first direction. The first gate structure, the second gate structure and the third gate structure are disposed on the substrate, and are separated from each other along the first direction and extend respectively along a second direction and a third direction. The first gate includes first, second and third island structures respectively extending along the third direction and separated from each other along the second direction. The third gate structure includes fourth, fifth and sixth island structures respectively extending along the third direction and separated from each other along the second direction.

公开(公告)号：US20230097416A1

公开(公告)日：2023-03-30

申请号：US17488128

申请日：2021-09-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting LUE ,  Wei-Chen CHEN

IPC: H01L27/11582 ,  H01L27/11556 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26

Abstract: Disclosed is 3D flash memory comprises a gate stack structure, an annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base, and comprising a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrating through the gate stack structure. The first source/drain pillar and the second source/drain pillar, disposed on the dielectric base, located within the annular channel pillar and penetrating through the gate stack structure, wherein the first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the annular channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the annular channel pillar. The first source/drain pillar and the second source/drain pillar are P-type doped.

公开(公告)号：US20220093688A1

公开(公告)日：2022-03-24

申请号：US17024968

申请日：2020-09-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting LUE

IPC: H01L27/24 ,  H01L45/00

Abstract: A semiconductor device includes a substrate, a stack, a conductive pillar, a memory layer, and a salicide layer. The stack is disposed on the substrate, wherein the stack includes a plurality of insulating layers and a plurality of conductive layers that are alternately stacked along a first direction. The conductive pillar penetrates the stack along the first direction. The memory layer surrounds the conductive pillar. The salicide layer surrounds the conductive pillar, wherein the memory layer is disposed between the conductive pillar and the salicide layer.

公开(公告)号：US20220068957A1

公开(公告)日：2022-03-03

申请号：US17009968

申请日：2020-09-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao YEH ,  Chih-Wei HU ,  Hang-Ting LUE ,  Guan-Ru LEE

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/522

Abstract: A memory device is provided. The memory device includes a stacked structure, a tubular element, a conductive pillar and memory cells. The tubular element includes a dummy channel layer and penetrates the stacked structure. The conductive pillar is enclosed by the tubular element and extending beyond a bottom surface of the dummy channel layer. The memory cells are in the stacked structure and electrically connected to the conductive pillar.

公开(公告)号：US20210074726A1

公开(公告)日：2021-03-11

申请号：US16989584

申请日：2020-08-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting LUE

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159 ,  G11C11/22 ,  G11C8/14 ,  G11C7/18

Abstract: A 3D flash memory is provided to includes a gate stack structure comprising a plurality of gate layers electrically insulated from each other, a cylindrical channel pillar vertically extending through each gate layer of the gate stack structure, a first conductive pillar vertically extending through the gate stack structure, the first conductive pillar being located within the cylindrical channel pillar and being electrically connected to the cylindrical channel pillar, and a second conductive pillar extending through the gate stack structure, the second conductive pillar being located within the cylindrical channel pillar and being electrically connected to the cylindrical channel pillar, the first conductive pillar and the second conductive pillar being separated from each other. The 3D flash memory also includes a ferroelectric layer disposed between gate layers of the gate stack structure and the cylindrical channel pillar.

公开(公告)号：US20200210102A1

公开(公告)日：2020-07-02

申请号：US16232119

申请日：2018-12-26

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hung-Sheng CHANG ,  Hang-Ting LUE ,  Yuan-Hao CHANG

IPC: G06F3/06

Abstract: A flash memory device and a controlling method are provided. The flash memory device includes a memory array, an in-place update module, an out-of-place update module and a latency-aware module. The in-place update module is used for performing a program procedure or a garbage collection procedure via a bit erase operation or a page erase operation on the memory array. The out-of-place update module is used for performing the program procedure or the garbage collection procedure via a block erase operation or a migration operation on the memory array. The latency-aware module is used for determining a relationship between a first overhead of the in-place update module and a second overhead of the out-of-place update module.

公开(公告)号：US20160365407A1

公开(公告)日：2016-12-15

申请号：US14739717

申请日：2015-06-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting LUE ,  Teng-Hao YEH

IPC: H01L49/02 ,  H01L27/06 ,  H01L27/115

CPC classification number: H01L28/90 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L28/60

Abstract: An integrated circuit includes a 3D NAND memory array with a stack of conductive strips and a capacitor with a stack of capacitor terminal strips. Multiple conductive strips in the stack of conductive strips, and multiple capacitor terminal strips of the stack of capacitor terminal strips, share a same plurality of plane positions relative to the substrate. Different plane positions in the same plurality of plane positions characterize different capacitor terminal strips in the stack of capacitor terminal strips and different conductive strips in the stack of conductive strips, and a same plane position characterizing both a conductive strip in the stack of conductive strips and a capacitor terminal strip in the stack of capacitor terminal strips indicates that the conductive strip and the capacitor terminal strip have a same vertical position relative to each other.

Abstract translation: 集成电路包括具有导电条的堆叠的3D NAND存储器阵列和具有堆叠的电容器端子条的电容器。 导电带堆叠中的多个导电条和电容器端子条的堆叠的多个电容器端子条相对于基板共享相同的多个平面位置。 在相同多个平面位置中的不同平面位置表示电容器端子条的堆叠中的不同的电容器端子条和导电条的堆叠中的不同的导电条，以及表征导电条的堆叠中的导电条的同一平面位置 电容器端子排堆叠中的电容器端子条表示导电条和电容器端子条相对于彼此具有相同的垂直位置。

公开(公告)号：US20150263173A1

公开(公告)日：2015-09-17

申请号：US14209011

申请日：2014-03-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting LUE

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7856 ,  H01L29/1041 ,  H01L29/7833 ,  H01L29/7851

Abstract: A high-voltage circuit is described that comprises a high-voltage finFET can have a semiconductor fin with an insulating cap on the fin. A gate dielectric is disposed on the first and second sides of the second. A gate overlies the gate dielectric and a channel region in the fin on the first and second sides, and over the cap. Source/drain terminals are disposed on opposing sides of the gate in the fin, and can include lightly doped regions that extend away from the edge of the gate to more highly doped contacts. The dimensions of the structures can be configured so that the transistor has a breakdown voltage of 30 V or higher.

Abstract translation: 描述了一种高压电路，其包括高压finFET可以具有在翅片上具有绝缘帽的半导体翅片。 栅电介质设置在第二侧的第一和第二侧上。 栅极覆盖栅极电介质和第一和第二侧上的鳍中的沟道区域，并且在盖上方。 源极/漏极端子设置在鳍中的栅极的相对侧上，并且可以包括从栅极的边缘延伸到更高掺杂的触点的轻掺杂区域。 可以配置结构的尺寸，使得晶体管具有30V或更高的击穿电压。

公开(公告)号：US20140361369A1

公开(公告)日：2014-12-11

申请号：US14163639

申请日：2014-01-24

Applicant: Macronix International Co., Ltd.

Inventor： Hang-Ting LUE ,  Wei-Chen CHEN

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L29/78645 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/092 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/66484 ,  H01L29/7391

Abstract: A dual-mode transistor structure comprises a semiconductor body. The semiconductor body of the device includes a channel region, a p-type terminal region (operable as a source or drain) adjacent a first side of the channel region and an n-type terminal region (operable as a source or drain) adjacent a second side of the channel region. A gate insulator is disposed on a surface of the semiconductor body over the channel region. A gate is disposed on the gate insulator over the channel region. A first assist gate is disposed on a first side of the gate, and a second assist gate is disposed on a second side of the gate. Optionally, a back gate can be included beneath the channel region. Biasing the assist gates can be used to select n-channel or p-channel modes in a single device.

Abstract translation: 双模式晶体管结构包括半导体本体。 器件的半导体本体包括与沟道区的第一侧相邻的沟道区，p型端子区（可操作为源极或漏极）和邻近沟道区的n型端子区域（可用作源极或漏极） 通道区域的第二侧。 栅极绝缘体设置在沟道区域上的半导体本体的表面上。 栅极设置在沟道区域上的栅极绝缘体上。 第一辅助栅极设置在栅极的第一侧上，第二辅助栅极设置在栅极的第二侧上。 可选地，可以在通道区域下面包括后门。 可以使用偏置辅助栅极在单个器件中选择n沟道或p沟道模式。

公开(公告)号：US20240386976A1

公开(公告)日：2024-11-21

申请号：US18199308

申请日：2023-05-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting LUE ,  Teng-Hao YEH ,  Wei-Chen CHEN

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30

Abstract: An array of memory cells includes a resistive component disposed in thermal communication with a group of memory cells in the array of memory cells. A capacitor and a circuit to cause discharge of the capacitor via the resistive component induces thermal anneal of the group of memory cells. A charge pump and a circuit to enable the charge pump to precharge the capacitor can be used. The charge pump, the capacitor and the array of memory cells can be disposed on a single integrated circuit. The group of memory cells can be arranged in a 3D stack having multiple levels, and the resistive component can be “snaked” through the stack. The thermal anneal can be executing in timing coordination with erase operations in flash memory.