公开(公告)号：US20160028613A1

公开(公告)日：2016-01-28

申请号：US14337334

申请日：2014-07-22

Applicant: Mellanox Technologies Ltd.

Inventor： Zachy Haramaty ,  Benny Koren ,  Eitan Zahavi ,  Barak Gafni ,  Tamir Ronen

IPC: H04L12/733 ,  H04L12/721

CPC classification number: H04L45/122 ,  H04L45/14

Abstract: A communication network includes multiple nodes, which are arranged in groups such that the nodes in each group are interconnected in a bipartite topology and the groups are interconnected in a mesh topology. The nodes are configured to convey traffic between source hosts and respective destination hosts by routing packets among the nodes on paths that do not traverse any intermediate hosts other than the source and destination hosts.

Abstract translation: 通信网络包括多个节点，这些节点被分组布置，使得每个组中的节点以二分之一拓扑互连，并且组以网状拓扑互连。 节点被配置为通过在不经过源主机和目的主机之外的任何中间主机的路径上的节点之间路由分组来在源主机和相应的目的主机之间传送流量。

公开(公告)号：US20250038871A1

公开(公告)日：2025-01-30

申请号：US18914324

申请日：2024-10-14

Applicant: Mellanox Technologies, Ltd.

Inventor： Liron Mula ,  Elad Mentovich ,  Paraskevas Bakopoulos ,  Eitan Zahavi ,  Sagi Kuks

IPC: H04J3/06 ,  H04Q11/00

Abstract: A system includes multiple processors to communicate with one another at predefined time slots. A given processor among the processors is to (i) hold a predetermined schedule plan that specifies which of the other processors in the system are accessible to the given processor at which of the time slots, the predetermined schedule plan having been determined before receiving data for transmission from the given processors to the other processors, (ii) queue data that is destined to one or more of the other processors, and (iii) transmit the queued data in accordance with the predetermined schedule plan.

公开(公告)号：US20240373378A1

公开(公告)日：2024-11-07

申请号：US18143509

申请日：2023-05-04

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Ran Ravid ,  Guy Lederman ,  Liron Mula ,  Eitan Zahavi ,  Peter Paneah

IPC: H04W56/00

Abstract: A system including a device coupled with a link and including a transmitter. The device is to generate a control block for synchronization via a physical layer of the link, the control block including a header portion of bits corresponding to a header indicating the message is a control block and a data portion of bits including synchronization information for synchronizing via the physical layer. The device is further to transmit, via the link, the control block comprising the header portion of bits and the data portion of bits.

公开(公告)号：US20240291749A1

公开(公告)日：2024-08-29

申请号：US18113240

申请日：2023-02-23

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Michael Avimelech Gandelman Milgrom ,  Lior Hodaya Bezen ,  Alex Netes ,  Yoav Menes ,  Guy Rozenberg Kunievsky ,  Vladimir Koushnir ,  Lion Levi ,  Eitan Zahavi

IPC: H04L45/00 ,  H04L45/745 ,  H04L47/2416 ,  H04L49/111

CPC classification number: H04L45/26 ,  H04L45/745 ,  H04L47/2416 ,  H04L49/111

Abstract: A networking device and system are described, among other things. An illustrative system is disclosed to include a switch programmed to route a received packet to an egress port based on a combination of a destination address associated with the received packet and an identification of an ingress port from which the packet was received by the switch.

公开(公告)号：US20240121158A1

公开(公告)日：2024-04-11

申请号：US17984424

申请日：2022-11-10

Applicant: Mellanox Technologies, Ltd.

Inventor： Paraskevas Bakopoulos ,  Dimitrios Kalavrouziotis ,  Nikolaos Argyris ,  Ioannis (Giannis) Patronas ,  Elad Mentovich ,  Eitan Zahavi ,  Prethvi Ramesh Kashinkunti ,  Louis Bennie Capps, JR. ,  Julie Irene Marcelle Bernauer ,  James Steven Fields, JR.

IPC: H04L41/12 ,  H04L49/45

CPC classification number: H04L41/12 ,  H04L49/45

Abstract: Apparatuses, systems, and methods are provided for scalable networking systems. An example system includes a plurality of core switches and a first stage patch panel associated with operation of a first set of network ports. In an operational configuration in which the first stage patch panel is coupled with the plurality of core switches, the first stage patch panel is configured to operatively couple the first set of network ports and a first portion of the plurality of core switches such that signals may pass therebetween. Furthermore, the first stage patch panel may preclude communication to a remaining portion of the plurality of core switches. The system may include a second stage patch panel associated with a second set of network ports that is operatively coupled with the plurality of core switches in the absence of the first stage patch panel so as to scale the networking system.

公开(公告)号：US20240098040A1

公开(公告)日：2024-03-21

申请号：US17982895

申请日：2022-11-08

Applicant: Mellanox Technologies, Ltd.

Inventor： Ioannis (Giannis) Patronas ,  Paraskevas Bakopoulos ,  Dimitrios Syrivelis ,  Nikolaos Argyris ,  Elad Mentovich ,  Louis Bennie Capps, JR. ,  Prethvi Ramesh Kashinkunti ,  Julie Irene Marcelle Bernauer ,  Eitan Zahavi

IPC: H04L49/55 ,  H04L49/00

CPC classification number: H04L49/557 ,  H04L49/30 ,  H04L49/555

Abstract: Systems, apparatuses, and methods are provided for resilience in network communications. An example system includes at least one first network port including a first plurality of subports and at least one second network port including a second plurality of subports. The system also includes an intermediate switch communicably connected to the at least one first network port and the at least one second network port. At least one of the first plurality of subports includes at least one first offline subport that is inoperable in an instance in which each of the remaining first plurality of subports are operable. The intermediate switch is configured to route communication from one of the second plurality of subports to the at least one first offline subport in an instance in which the intermediate switch receives an indication of a malfunction associated with the first plurality of subports.

公开(公告)号：US20240098039A1

公开(公告)日：2024-03-21

申请号：US17982827

申请日：2022-11-08

Applicant: Mellanox Technologies, Ltd.

Inventor： Ioannis (Giannis) Patronas ,  Paraskevas Bakopoulos ,  Dimitrios Syrivelis ,  Nikolaos Argyris ,  Elad Mentovich ,  Louis Bennie Capps, JR. ,  Prethvi Ramesh Kashinkunti ,  Julie Irene Marcelle Bernauer ,  Eitan Zahavi

IPC: H04L49/55

CPC classification number: H04L49/557

Abstract: Systems and methods for resilience in network communications are provided. An example system includes a first network port pair including a first input network port and a first output network port. The system further includes an intermediate switch configured to communicably connect the first input network port and the first output network port and a first redundant network port communicably connected with the intermediate switch. The intermediate switch establishes communication between the first input network port and the first redundant network port in an instance in which the intermediate switch receives an indication of a malfunction associated with the first output network port or establishes communication between the first output network port and the first redundant network port in an instance in which the intermediate switch receives an indication of a malfunction associated with the first input network port.

公开(公告)号：US11909710B2

公开(公告)日：2024-02-20

申请号：US17859022

申请日：2022-07-07

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Eitan Zahavi ,  Guy Rozenberg ,  Matty Kadosh ,  Lion Levi ,  Boris Pismenny ,  Alex Netes ,  Miriam Menes ,  Lior Hodaya Bezen ,  Michael Tahar

IPC: H04L61/106 ,  H04L61/5061 ,  H04L61/5092

CPC classification number: H04L61/106 ,  H04L61/5061 ,  H04L61/5092

Abstract: A method for communication includes provisioning each node in a network with a respective set of two or more network addresses. Each node in succession is assigned a respective network address from the respective provisioned set that has not been assigned for use by any preceding node. Upon finding for a given node that all the network addresses in the respective provisioned set were assigned to preceding nodes, the preceding nodes are searched to identify a candidate node having an additional network address in the respective provisioned set, other than the assigned respective network address, that was not yet assigned to any of the nodes. The additional network address is assigned to the candidate node instead of the respective network address that was previously assigned to the candidate node, and the assigning of the network addresses to the nodes in the succession resumes following the candidate node.

公开(公告)号：US11853116B2

公开(公告)日：2023-12-26

申请号：US17582058

申请日：2022-01-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko ,  Eitan Zahavi ,  Natan Manevich ,  Bar Shapira

IPC: G06F1/14 ,  H04J3/06 ,  G06F1/12

CPC classification number: G06F1/14 ,  G06F1/12 ,  H04J3/0661 ,  H04J3/0679 ,  H04J3/0682 ,  H04J3/0697

Abstract: In one embodiment, a device includes a hardware clock to maintain a clock value, a hardware counter to maintain an estimation of a dynamic error bound of the clock value, and a clock controller to intermittently discipline the hardware clock responsively to a remote clock, advance the hardware counter at a rate responsively to a clock drift, and adjust the hardware counter responsively to the hardware clock being disciplined.

公开(公告)号：US20220407822A1

公开(公告)日：2022-12-22

申请号：US17779157

申请日：2019-11-28

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ioannis (Giannis) Patronas ,  Paraskevas Bakopoulos ,  Eitan Zahavi ,  Eran Aharon ,  Elad Mentovich

IPC: H04L49/253

Abstract: A routing controller (30) includes an interface (68) and multiple processors (60) The interface is configured to receive a permutation (76) defining requested interconnections between N input ports and N output ports of a Benes network (24). The Benes network includes multiple 2-by-2 switches (42), and is reducible in a plurality of nested subnetworks associated with respective nesting levels, down to irreducible subnetworks including a single 2-by-2 switch. The multiple processors are configured to collectively determine a setting of the 2-by-2 switches that implements the received permutation, including determining sub-settings for two or more subnetworks of a given nesting level in parallel, and to configure the multiple 2-by-2 switches of the Benes network in accordance with the determined setting.