公开(公告)号：US10541019B2

公开(公告)日：2020-01-21

申请号：US15968297

申请日：2018-05-01

Applicant: Micron Technology, Inc.

Inventor： Dean Gans

IPC: G11C5/14 ,  G11C11/4074 ,  G11C11/4076

Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a first power supply having a first fixed voltage, a second power supply having a second fixed voltage, a plurality of circuits coupled to the first power supply via a first switch and the second power supply via a second switch, and a power control circuit configured to selectively enable one of the first switch and the second switch responsive to power demand information.

公开(公告)号：US10394473B2

公开(公告)日：2019-08-27

申请号：US15683540

申请日：2017-08-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean Gans

IPC: G06F13/36 ,  G11C7/00 ,  G06F3/06 ,  G06F13/368 ,  G11C7/10 ,  G06F13/16

Abstract: An arbitration system and method is disclosed. The apparatus includes a first and a second memory devices, and a resistor coupled in common to the first and second memory devices, the first memory device includes a first calibration circuit configured to perform a first calibration operation responsive, at least in part, to an external calibration command, the first calibration operation being performed based on the resistor, and the second memory device includes a second calibration circuit configured to perform a second calibration operation responsive, at least in part, to the external calibration command, the second calibration operation being performed based on the resistor after the first calibration operation has finished.

公开(公告)号：US10115449B2

公开(公告)日：2018-10-30

申请号：US15415655

申请日：2017-01-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean Gans ,  Moo Sung Chae ,  Daniel Skinner

IPC: G11C7/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/4093

Abstract: A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.

公开(公告)号：US09965408B2

公开(公告)日：2018-05-08

申请号：US14712610

申请日：2015-05-14

Applicant: Micron Technology, Inc.

Inventor： Dean Gans ,  Bruce Schober ,  Moo Sung Chae

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1689 ,  G06F13/4068

Abstract: Apparatuses and methods for asymmetric input/output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The receiver may be configured to receive first data signals having a first voltage swing and having a first slew rate. The transmitter may be configured to provide second data signals having a second voltage swing and having a second slew rate, wherein the first and second voltage swings are different, and wherein the first and second slew rates are different.

公开(公告)号：US09766831B2

公开(公告)日：2017-09-19

申请号：US14883454

申请日：2015-10-14

Applicant: Micron Technology, Inc.

Inventor： Dean Gans

IPC: G06F13/36 ,  G11C7/00 ,  G06F3/06 ,  G06F13/368 ,  G11C7/10 ,  G06F13/16

CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/0683 ,  G06F13/1668 ,  G06F13/368 ,  G11C7/1051 ,  G11C2207/2254

Abstract: An arbitration system and method is disclosed. The apparatus includes a first and a second memory devices, and a resistor coupled in common to the first and second memory devices, the first memory device includes a first calibration circuit configured to perform a first calibration operation responsive, at least in part, to an external calibration command, the first calibration operation being performed based on the resistor, and the second memory device includes a second calibration circuit configured to perform a second calibration operation responsive, at least in part, to the external calibration command, the second calibration operation being performed based on the resistor after the first calibration operation has finished.

公开(公告)号：US20170109091A1

公开(公告)日：2017-04-20

申请号：US14883454

申请日：2015-10-14

Applicant: Micron Technology, Inc.

Inventor： Dean Gans

IPC: G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/0683 ,  G06F13/1668 ,  G06F13/368 ,  G11C7/1051 ,  G11C2207/2254

Abstract: An arbitration system and method is disclosed. The apparatus includes a fiat and a second memory devices, and a resistor coupled in common to the first and second memory devices, the first memory device includes a first calibration circuit configured to perform a first calibration operation responsive, at least in part, to an external calibration command, the first calibration operation being performed based on the resistor, and the second memory device includes a second calibration circuit configured to perform a second calibration operation responsive, at least in part, to the external calibration command, the second calibration operation being performed based on the resistor after the first calibration operation has finished.

公开(公告)号：US09601182B2

公开(公告)日：2017-03-21

申请号：US14707878

申请日：2015-05-08

Applicant: Micron Technology, Inc.

Inventor： Dean Gans ,  Moo Sung Chae ,  Daniel Skinner

IPC: G11C7/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C7/10 ,  G11C7/14 ,  G11C7/06

CPC classification number: G11C11/4076 ,  G11C7/062 ,  G11C7/1006 ,  G11C7/14 ,  G11C7/222 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.

公开(公告)号：US20220334986A1

公开(公告)日：2022-10-20

申请号：US17751298

申请日：2022-05-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Dean Gans

IPC: G06F13/16 ,  G06F9/30 ,  G11C7/22 ,  G11C29/02

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

公开(公告)号：US11347666B2

公开(公告)日：2022-05-31

申请号：US17032152

申请日：2020-09-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Dean Gans

IPC: G06F13/16 ,  G06F9/30 ,  G11C7/22 ,  G11C29/02

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

公开(公告)号：US11121714B2

公开(公告)日：2021-09-14

申请号：US16799668

申请日：2020-02-24

Applicant: Micron Technology, Inc.

Inventor： Dean Gans

IPC: H03K19/0185 ,  G11C29/02 ,  G11C29/50 ,  G11C7/02 ,  G06F13/40 ,  H03K19/00 ,  G11C7/04 ,  G11C29/44

Abstract: Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance are disclosed. A memory device of a semiconductor device may be set in an identification mode and provide an identification request to other memory devices that are coupled to a common communication channel. The memory devices that are coupled to the common communication channel may share an external resistance, for example, for calibration of respective programmable termination components of the memory devices. The memory devices that receive the identification request set a respective identification flag which can be read to determine which memory devices share an external resistance with the memory device having the set identification mode.