公开(公告)号：US20220392914A1

公开(公告)日：2022-12-08

申请号：US17819009

申请日：2022-08-11

Applicant: Micron Technology, Inc.

Inventor： Umberto Maria Meotto ,  Emilio Camerlenghi ,  Paolo Tessariol ,  Luca Laurin

IPC: H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L23/544 ,  H01L27/1157

Abstract: A method of forming a microelectronic device comprises forming a memory array region comprising memory cells vertically over a base structure comprising a semiconductive material and alignment mark structures vertically extending into the semiconductive material. First contact structures are formed to extend through the memory array region and into the alignment mark structures. A support structure is formed over the memory array region. A portion of the base structure is removed to expose the alignment mark structures. A control logic region is formed vertically adjacent a remaining portion of the base structure. The control logic region comprises control logic devices in electrical communication with the first contact structures by way of second contact structures extending partially through the alignment mark structures and contacting the first contact structures. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.

公开(公告)号：US11514953B2

公开(公告)日：2022-11-29

申请号：US17243937

申请日：2021-04-29

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Paolo Tessariol ,  David H. Wells ,  Lars P. Heineck ,  Richard J. Hill ,  Lifang Xu ,  Indra V. Chary ,  Emilio Camerlenghi

IPC: G11C11/34 ,  G11C5/06 ,  H01L21/50 ,  H01L27/11582 ,  H01L27/11556 ,  H01L25/065

Abstract: Some embodiments include an integrated assembly having a pair of adjacent memory-block-regions, and having a separator structure between the adjacent memory-block-regions. The memory-block-regions include a first stack of alternating conductive levels and first insulative levels. The separator structure includes a second stack of alternating second and third insulative levels. The second insulative levels are substantially horizontally aligned with the conductive levels, and the third insulative levels are substantially horizontally aligned with the first insulative levels. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11417676B2

公开(公告)日：2022-08-16

申请号：US17000754

申请日：2020-08-24

Applicant: Micron Technology, Inc.

Inventor： Umberto Maria Meotto ,  Emilio Camerlenghi ,  Paolo Tessariol ,  Luca Laurin

IPC: H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L23/544 ,  H01L27/1157

Abstract: A method of forming a microelectronic device comprises forming a memory array region comprising memory cells vertically over a base structure comprising a semiconductive material and alignment mark structures vertically extending into the semiconductive material. First contact structures are formed to extend through the memory array region and into the alignment mark structures. A support structure is formed over the memory array region. A portion of the base structure is removed to expose the alignment mark structures. A control logic region is formed vertically adjacent a remaining portion of the base structure. The control logic region comprises control logic devices in electrical communication with the first contact structures by way of second contact structures extending partially through the alignment mark structures and contacting the first contact structures. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.

公开(公告)号：US11309039B2

公开(公告)日：2022-04-19

申请号：US17202398

申请日：2021-03-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Violante Moschiano ,  Tecla Ghilardi ,  Tommaso Vali ,  Emilio Camerlenghi ,  William C. Filipiak ,  Andrea D'Alessandro

IPC: G11C16/34 ,  G11C16/26 ,  G11C8/08 ,  G11C11/413 ,  G11C5/06

Abstract: Memories having a controller configured, during a pre-charge portion of a read operation, to apply a sequence of increasing voltage levels concurrently to each access line of a plurality of access lines, wherein each voltage level of the sequence of increasing voltage levels is higher than any previous voltage level of the sequence of increasing voltage levels and lower than any subsequent voltage level of the sequence of increasing voltage levels, and determine a particular voltage level of the sequence of increasing voltage levels corresponding to a point at which all memory cells of the plurality of strings of series-connected memory cells are first deemed to be activated while applying the sequence of increasing voltage levels.

公开(公告)号：US11094627B2

公开(公告)日：2021-08-17

申请号：US16663683

申请日：2019-10-25

Applicant: Micron Technology, Inc.

Inventor： Vladimir Machkaoutsan ,  Pieter Blomme ,  Emilio Camerlenghi ,  Justin B. Dorhout ,  Jian Li ,  Ryan L. Meyer ,  Paolo Tessariol

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11524 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. First dummy pillars in the memory blocks extend through at least a majority of the insulative tiers and the conductive tiers through which the channel-material strings extend. Second dummy pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The second dummy pillars extend through at least a majority of the insulative tiers and the conductive tiers through which the operative channel-material strings extend laterally-between the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.

公开(公告)号：US10950316B2

公开(公告)日：2021-03-16

申请号：US16990137

申请日：2020-08-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Violante Moschiano ,  Tecla Ghilardi ,  Tommaso Vali ,  Emilio Camerlenghi ,  William C. Filipiak ,  Andrea D'Alessandro

IPC: G11C16/26 ,  G11C16/34 ,  G11C5/06 ,  G11C11/413 ,  G11C8/08

Abstract: Apparatus having plurality of data lines each selectively connected to a respective string of series-connected memory cells, a plurality of registers each configured to indicate a state of a respective data line, and logic configured to indicate when each data line of the plurality of data lines has a particular state might facilitate determination of a pass voltage of a read operation.

公开(公告)号：US20210065810A1

公开(公告)日：2021-03-04

申请号：US16555050

申请日：2019-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Giovanni Maria Paolucci ,  Paolo Tessariol ,  Emilio Camerlenghi ,  Gianpietro Carnevale ,  Augusto Benvenuti

IPC: G11C16/16 ,  G11C16/24 ,  G11C16/04 ,  G11C16/30

Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.

公开(公告)号：US20200372961A1

公开(公告)日：2020-11-26

申请号：US16990137

申请日：2020-08-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Violante Moschiano ,  Tecla Ghilardi ,  Tommaso Vali ,  Emilio Camerlenghi ,  William C. Filipiak ,  Andrea D'Alessandro

IPC: G11C16/34 ,  G11C16/26 ,  G11C8/08 ,  G11C11/413 ,  G11C5/06

Abstract: Apparatus having plurality of data lines each selectively connected to a respective string of series-connected memory cells, a plurality of registers each configured to indicate a state of a respective data line, and logic configured to indicate when each data line of the plurality of data lines has a particular state might facilitate determination of a pass voltage of a read operation.

公开(公告)号：US10777286B2

公开(公告)日：2020-09-15

申请号：US16267488

申请日：2019-02-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Violante Moschiano ,  Tecla Ghilardi ,  Tommaso Vali ,  Emilio Camerlenghi ,  William C. Filipiak ,  Andrea D'Alessandro

IPC: G11C16/26 ,  G11C16/34 ,  G11C8/08 ,  G11C11/413 ,  G11C5/06

Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, ceasing increasing the voltage level applied to each access line of the plurality of access lines in response to the state of each data line of the plurality of data lines having a particular condition, changing a voltage level applied to a particular access line of the plurality of access lines to a particular voltage level, and sensing a state of each data line of a subset of the plurality of data lines while applying the particular voltage level to the particular access line.