公开(公告)号：US11762767B2

公开(公告)日：2023-09-19

申请号：US17302064

申请日：2021-04-22

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Giuseppina Puzzilli ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe ,  James Fitzpatrick ,  Shyam Sunder Raghunathan ,  Violante Moschiano ,  Tecla Ghilardi

IPC: G06F12/00 ,  G06F12/02 ,  G11C29/52 ,  G11C16/34 ,  G11C16/04

CPC classification number: G06F12/0269 ,  G11C16/3418 ,  G11C29/52 ,  G06F2212/702 ,  G11C16/0483

Abstract: A highly read data manager of a memory device receives a request to perform receives a request to perform a data relocation operation on a first wordline of a plurality of wordlines for a memory device, the memory device comprising a plurality of multi-level memory cells, wherein each multi-level memory cell comprises a plurality of pages; determines at the first wordline comprises data stored at one or more high read disturb pages of the plurality of pages; determines whether the data comprises a characteristic that satisfies a threshold criterion in relation to additional data stored on additional wordlines of the plurality of wordlines; responsive to determining that the data comprises the characteristic that satisfies the threshold criterion, identifies one or more low read disturb pages of the plurality of pages of a target wordline for relocating the data; and responsive to identifying the one or more low read disturb pages of the target wordline, stores at least a portion of the data at the one or more low read disturb pages of the target wordline.

公开(公告)号：US20200211660A1

公开(公告)日：2020-07-02

申请号：US16267488

申请日：2019-02-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Violante Moschiano ,  Tecla Ghilardi ,  Tommaso Vali ,  Emilio Camerlenghi ,  William C. Filipiak ,  Andrea D'Alessandro

IPC: G11C16/34 ,  G11C16/26 ,  G11C5/06 ,  G11C11/413 ,  G11C8/08

Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, ceasing increasing the voltage level applied to each access line of the plurality of access lines in response to the state of each data line of the plurality of data lines having a particular condition, changing a voltage level applied to a particular access line of the plurality of access lines to a particular voltage level, and sensing a state of each data line of a subset of the plurality of data lines while applying the particular voltage level to the particular access line.

公开(公告)号：US20220375522A1

公开(公告)日：2022-11-24

申请号：US17729989

申请日：2022-04-26

Applicant: Micron Technology, Inc.

Inventor： Tyler L. Betz ,  Tecla Ghilardi ,  Violante Moschiano

IPC: G11C15/04 ,  G11C11/406 ,  G11C11/4093 ,  G11C11/4096

Abstract: A memory system includes a memory device comprising a value data block a content addressable memory (CAM) block storing a plurality of stored search keys. The memory system further includes a processing device that receives an input search key, identifies, from the plurality of stored search keys in a CAM block of a memory device, multiple redundant copies of a stored search key that match the input search key, and determines a plurality of locations in a value data block, the plurality of locations corresponding to the multiple redundant copies, wherein one of the plurality of locations comprises a first timestamp and data representing a value associated with the input search key, and wherein a remainder of the plurality of locations comprises one or more additional timestamps. The processing device further determines whether the first timestamp matches the one or more additional timestamps, and responsive to the first timestamp matching the one or more additional timestamps, retries from the one of the plurality of locations, the data representing the value associated with the input search key.

公开(公告)号：US11955175B2

公开(公告)日：2024-04-09

申请号：US17729989

申请日：2022-04-26

Applicant: Micron Technology, Inc.

Inventor： Tyler L. Betz ,  Tecla Ghilardi ,  Violante Moschiano

IPC: G11C15/04 ,  G11C11/406 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G11C15/04 ,  G11C11/40615 ,  G11C11/4093 ,  G11C11/4096

Abstract: A memory system includes a memory device comprising a value data block a content addressable memory (CAM) block storing a plurality of stored search keys. The memory system further includes a processing device that receives an input search key, identifies, from the plurality of stored search keys in a CAM block of a memory device, multiple redundant copies of a stored search key that match the input search key, and determines a plurality of locations in a value data block, the plurality of locations corresponding to the multiple redundant copies, wherein one of the plurality of locations comprises a first timestamp and data representing a value associated with the input search key, and wherein a remainder of the plurality of locations comprises one or more additional timestamps. The processing device further determines whether the first timestamp matches the one or more additional timestamps, and responsive to the first timestamp matching the one or more additional timestamps, retries from the one of the plurality of locations, the data representing the value associated with the input search key.

公开(公告)号：US11751396B2

公开(公告)日：2023-09-05

申请号：US17648528

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Yifen Liu ,  Tecla Ghilardi ,  George Matamis ,  Justin D. Shepherdson ,  Nancy M. Lomeli ,  Chet E. Carter ,  Erik R. Byers

IPC: H10B43/27 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53257 ,  H01L23/53271 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20220139958A1

公开(公告)日：2022-05-05

申请号：US17648528

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Yifen Liu ,  Tecla Ghilardi ,  George Matamis ,  Justin D. Shepherdson ,  Nancy M. Lomeli ,  Chet E. Carter ,  Erik R. Byers

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US11264404B2

公开(公告)日：2022-03-01

申请号：US16904317

申请日：2020-06-17

Applicant: Micron Technology, Inc.

Inventor： Yifen Liu ,  Tecla Ghilardi ,  George Matamis ,  Justin D. Shepherdson ,  Nancy M. Lomeli ,  Chet E. Carter ,  Erik R. Byers

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20210202020A1

公开(公告)日：2021-07-01

申请号：US17202398

申请日：2021-03-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Violante Moschiano ,  Tecla Ghilardi ,  Tommaso Vali ,  Emilio Camerlenghi ,  William C. Filipiak ,  Andrea D'Alessandro

IPC: G11C16/34 ,  G11C16/26 ,  G11C8/08 ,  G11C11/413 ,  G11C5/06

Abstract: Memories having a controller configured, during a pre-charge portion of a read operation, to apply a sequence of increasing voltage levels concurrently to each access line of a plurality of access lines, wherein each voltage level of the sequence of increasing voltage levels is higher than any previous voltage level of the sequence of increasing voltage levels and lower than any subsequent voltage level of the sequence of increasing voltage levels, and determine a particular voltage level of the sequence of increasing voltage levels corresponding to a point at which all memory cells of the plurality of strings of series-connected memory cells are first deemed to be activated while applying the sequence of increasing voltage levels.

公开(公告)号：US20220342813A1

公开(公告)日：2022-10-27

申请号：US17302064

申请日：2021-04-22

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Giuseppina Puzzilli ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe ,  James Fitzpatrick ,  Shyam Sunder Raghunathan ,  Violante Moschiano ,  Tecla Ghilardi

IPC: G06F12/02 ,  G11C29/52 ,  G11C16/34

Abstract: A highly read data manager of a memory device receives a request to perform receives a request to perform a data relocation operation on a first wordline of a plurality of wordlines for a memory device, the memory device comprising a plurality of multi-level memory cells, wherein each multi-level memory cell comprises a plurality of pages; determines at the first wordline comprises data stored at one or more high read disturb pages of the plurality of pages; determines whether the data comprises a characteristic that satisfies a threshold criterion in relation to additional data stored on additional wordlines of the plurality of wordlines; responsive to determining that the data comprises the characteristic that satisfies the threshold criterion, identifies one or more low read disturb pages of the plurality of pages of a target wordline for relocating the data; and responsive to identifying the one or more low read disturb pages of the target wordline, stores at least a portion of the data at the one or more low read disturb pages of the target wordline.

公开(公告)号：US11309039B2

公开(公告)日：2022-04-19

申请号：US17202398

申请日：2021-03-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Violante Moschiano ,  Tecla Ghilardi ,  Tommaso Vali ,  Emilio Camerlenghi ,  William C. Filipiak ,  Andrea D'Alessandro

IPC: G11C16/34 ,  G11C16/26 ,  G11C8/08 ,  G11C11/413 ,  G11C5/06

Abstract: Memories having a controller configured, during a pre-charge portion of a read operation, to apply a sequence of increasing voltage levels concurrently to each access line of a plurality of access lines, wherein each voltage level of the sequence of increasing voltage levels is higher than any previous voltage level of the sequence of increasing voltage levels and lower than any subsequent voltage level of the sequence of increasing voltage levels, and determine a particular voltage level of the sequence of increasing voltage levels corresponding to a point at which all memory cells of the plurality of strings of series-connected memory cells are first deemed to be activated while applying the sequence of increasing voltage levels.