公开(公告)号：US11094627B2

公开(公告)日：2021-08-17

申请号：US16663683

申请日：2019-10-25

Applicant: Micron Technology, Inc.

Inventor： Vladimir Machkaoutsan ,  Pieter Blomme ,  Emilio Camerlenghi ,  Justin B. Dorhout ,  Jian Li ,  Ryan L. Meyer ,  Paolo Tessariol

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11524 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. First dummy pillars in the memory blocks extend through at least a majority of the insulative tiers and the conductive tiers through which the channel-material strings extend. Second dummy pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The second dummy pillars extend through at least a majority of the insulative tiers and the conductive tiers through which the operative channel-material strings extend laterally-between the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.

公开(公告)号：US20230343815A1

公开(公告)日：2023-10-26

申请号：US17726965

申请日：2022-04-22

Applicant: Micron Technology, Inc.

Inventor： Ryan L. Meyer ,  Vinay Nair ,  Andrea Gotti ,  Kevin Shea ,  Kyle R. Knori

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/60 ,  H01L27/1085

Abstract: Methods, apparatuses, and systems related to depositing a storage node material are described. An example method includes forming a semiconductor structure including a support structure having a first silicate material over a bottom nitride material, a first nitride material over the first silicate material, a second silicate material over the first nitride material, and a second nitride material over the second silicate material. The method further includes removing portions of the second nitride material. The method further includes depositing a third silicate material over the second nitride material and a portion of the second silicate material. The method further includes forming an opening through the semiconductor structure. The method further includes depositing a storage node material within the opening.

公开(公告)号：US20210125919A1

公开(公告)日：2021-04-29

申请号：US16663683

申请日：2019-10-25

Applicant: Micron Technology, Inc.

Inventor： Vladimir Machkaoutsan ,  Pieter Blomme ,  Emilio Camerlenghi ,  Justin B. Dorhout ,  Jian Li ,  Ryan L. Meyer ,  Paolo Tessariol

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. First dummy pillars in the memory blocks extend through at least a majority of the insulative tiers and the conductive tiers through which the channel-material strings extend. Second dummy pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The second dummy pillars extend through at least a majority of the insulative tiers and the conductive tiers through which the operative channel-material strings extend laterally-between the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.

公开(公告)号：US11563011B2

公开(公告)日：2023-01-24

申请号：US17038799

申请日：2020-09-30

Applicant: Micron Technology, Inc.

Inventor： Vinay Nair ,  Silvia Borsari ,  Ryan L. Meyer ,  Russell A. Benson ,  Yi Fang Lee

IPC: H01L27/108 ,  G11C5/10 ,  G11C11/402

Abstract: A method used in forming integrated circuitry comprises forming conductive material over a substrate. The conductive material is patterned into a conductive line that is horizontally longitudinally elongated. The conductive material is vertically recessed in longitudinally-spaced first regions of the conductive line to form longitudinally-spaced conductive pillars that individually are in individual longitudinally-spaced second regions that longitudinally-alternate with the longitudinally-spaced first regions along the conductive line. The conductive pillars project vertically relative to the conductive material in the longitudinally-spaced and vertically-recessed first regions of the conductive line. Electronic components are formed directly above the conductive pillars. Individual of the electronic components are directly electrically coupled to individual of the conductive pillars. Additional methods, including structure independent of method, are disclosed.

公开(公告)号：US20220130857A1

公开(公告)日：2022-04-28

申请号：US17567287

申请日：2022-01-03

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Justin B. Dorhout ,  Jian Li ,  Ryan L. Meyer

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/1157

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The pillars are directly against conducting material of conductive lines in the conductive tiers. Other arrays, and methods, are disclosed.

公开(公告)号：US20220102348A1

公开(公告)日：2022-03-31

申请号：US17038799

申请日：2020-09-30

Applicant: Micron Technology, Inc.

Inventor： Vinay Nair ,  Silvia Borsari ,  Ryan L. Meyer ,  Russell A. Benson ,  Yi Fang Lee

IPC: H01L27/108 ,  G11C11/402 ,  G11C5/10

Abstract: A method used in forming integrated circuitry comprises forming conductive material over a substrate. The conductive material is patterned into a conductive line that is horizontally longitudinally elongated. The conductive material is vertically recessed in longitudinally-spaced first regions of the conductive line to form longitudinally-spaced conductive pillars that individually are in individual longitudinally-spaced second regions that longitudinally-alternate with the longitudinally-spaced first regions along the conductive line. The conductive pillars project vertically relative to the conductive material in the longitudinally-spaced and vertically-recessed first regions of the conductive line. Electronic components are formed directly above the conductive pillars. Individual of the electronic components are directly electrically coupled to individual of the conductive pillars. Additional methods, including structure independent of method, are disclosed.

公开(公告)号：US11792991B2

公开(公告)日：2023-10-17

申请号：US17567287

申请日：2022-01-03

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Justin B. Dorhout ,  Jian Li ,  Ryan L. Meyer

IPC: H01L21/768 ,  H01L23/522 ,  H10B43/27 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The pillars are directly against conducting material of conductive lines in the conductive tiers. Other arrays, and methods, are disclosed.

公开(公告)号：US11244955B2

公开(公告)日：2022-02-08

申请号：US16550244

申请日：2019-08-25

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Justin B. Dorhout ,  Jian Li ,  Ryan L. Meyer

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The pillars are directly against conducting material of conductive lines in the conductive tiers. Other arrays, and methods, are disclosed.

公开(公告)号：US20210343640A1

公开(公告)日：2021-11-04

申请号：US17374634

申请日：2021-07-13

Applicant: Micron Technology, Inc.

Inventor： Vladimir Machkaoutsan ,  Pieter Blomme ,  Emilio Camerlenghi ,  Justin B. Dorhout ,  Jian Li ,  Ryan L. Meyer ,  Paolo Tessariol

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11524 ,  H01L21/311

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. First dummy pillars in the memory blocks extend through at least a majority of the insulative tiers and the conductive tiers through which the channel-material strings extend. Second dummy pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The second dummy pillars extend through at least a majority of the insulative tiers and the conductive tiers through which the operative channel-material strings extend laterally-between the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.

公开(公告)号：US20210057439A1

公开(公告)日：2021-02-25

申请号：US16550244

申请日：2019-08-25

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Justin B. Dorhout ,  Jian Li ,  Ryan L. Meyer

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The pillars are directly against conducting material of conductive lines in the conductive tiers. Other arrays, and methods, are disclosed.