公开(公告)号：US10217524B2

公开(公告)日：2019-02-26

申请号：US15412148

申请日：2017-01-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Francesco Falanga ,  Victor Tsai

IPC: G11C29/00 ,  G11C29/38 ,  G11C16/34 ,  G11C29/52 ,  G11C29/44 ,  G11C16/04 ,  G11C29/36 ,  G11C29/04

Abstract: Methods of managing systems comprising a processor and a memory device external to the processor, including exposing the memory device to temperature levels associated with soldering, starting up the memory device and testing pre-programmed data using control circuitry of the memory device. When results of the testing indicate repair of the pre-programmed data should be performed, issuing a command from the processor to the memory device indicative of a desire for the memory device to repair the pre-programmed data, and in response to the memory device receiving the command, repairing the pre-programmed data using the control circuitry of the memory device.

公开(公告)号：US20150082104A1

公开(公告)日：2015-03-19

申请号：US14552863

申请日：2014-11-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Francesco Falanga ,  Victor Tsai

IPC: G11C29/44 ,  G11C29/38

CPC classification number: G11C29/38 ,  G11C16/0483 ,  G11C16/3418 ,  G11C29/36 ,  G11C29/4401 ,  G11C29/52 ,  G11C2029/0407 ,  G11C2029/0409

Abstract: Memory devices storing particular data, systems containing such memory devices and methods of testing such memory devices. The memory devices include an array of memory cells containing particular data, and control circuitry configured to control operations of the array of memory cells. The control circuitry is further configured to perform a test of the particular data in response to a command received from an external device and perform a repair of the particular data when results of the test indicate that repair of the particular data is needed

Abstract translation: 存储特定数据的存储器件，包含这种存储器件的系统以及测试这样的存储器件的方法。 存储器件包括包含特定数据的存储器单元的阵列，以及被配置为控制存储器单元阵列的操作的控制电路。 控制电路还被配置为响应于从外部设备接收的命令来执行特定数据的测试，并且当测试结果指示需要修复特定数据时执行特定数据的修复

公开(公告)号：US11847468B2

公开(公告)日：2023-12-19

申请号：US17645687

申请日：2021-12-22

Applicant: Micron Technology, Inc.

Inventor： Francesco Basso ,  Luca Porzio ,  Roberto Izzi ,  Francesco Falanga ,  Nadav Grosz ,  Massimo Iaculo

IPC: G06F9/4401 ,  G06F3/06

CPC classification number: G06F9/4406 ,  G06F3/061 ,  G06F3/0644 ,  G06F3/0683

Abstract: Methods, systems, and devices for data defragmentation for a system boot procedure are described. The memory system may determine a write random index associated with a boot procedure. The write random index may indicate a relationship between a first quantity of sequential logical addresses accessed as part of the boot procedure and a second quantity of random logical addresses accessed as part of the boot procedure. The memory system may determine whether the write random index satisfies a threshold based on determining the write random index. In some cases, the memory system may transfer, to a second portion of the memory system, data stored in a first portion of the memory system based on determining that the write random index satisfies the threshold. The memory system may receive a request to perform the boot procedure after transferring the data and output, to the host system, the data transferred.

公开(公告)号：US11789661B2

公开(公告)日：2023-10-17

申请号：US17747477

申请日：2022-05-18

Applicant: Micron Technology, Inc.

Inventor： Angelo Della Monica ,  Eric Kwok Fung Yuen ,  Pasquale Cimmino ,  Massimo Iaculo ,  Francesco Falanga

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0632 ,  G06F3/0644 ,  G06F3/0679

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which functionalities of a memory device of the apparatus can be extended by changing data flow behaviour associated with standard commands used between a host platform and the memory device. Such functionalities can include debug capabilities. In an embodiment, a standard write command and data using a standard protocol to write to a memory device is received in the memory device, where the data is setup information to enable an extension component in the memory device. An extension component includes instructions in the memory device to execute operations on components of the memory device. The memory device can execute operations of the enabled extension component in the memory device based on the setup information. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US11586547B2

公开(公告)日：2023-02-21

申请号：US16883769

申请日：2020-05-26

Applicant: Micron Technology, Inc.

Inventor： Crescenzo Attanasio ,  Massimo Iaculo ,  Pasquale Cimmino ,  Nicola Cavaliere ,  Francesco Falanga

IPC: G06F12/00 ,  G06F12/0875 ,  G06F9/30

Abstract: Methods, systems, and devices for an enhanced instruction caching scheme are described. A memory controller may include a first closely-coupled memory component that is associated with storing data and control information and a second closely-coupled memory component that is associated with storing control information. The memory controller may be configured to retrieve data from the first memory closely-coupled component and control information from a second closely-coupled memory component. Control information may be stored in the first closely-coupled memory component, and a memory controller may access the control information stored in the first closely-coupled memory component by transferring, from the first closely-coupled memory component, the control information into the second closely-coupled memory component. After transferring the control information into the second closely-coupled memory component, the memory controller may access the control information from the second closely-coupled memory component.

公开(公告)号：US11275508B2

公开(公告)日：2022-03-15

申请号：US16361445

申请日：2019-03-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Francesco Falanga ,  Danilo Caraccio

IPC: G06F3/06 ,  G06F12/02

Abstract: Methods for automatically performing a background operation in a memory device might include automatically performing the background operation responsive to automatic performance of the background operation being enabled and receiving a start command.

公开(公告)号：US10754580B2

公开(公告)日：2020-08-25

申请号：US15790690

申请日：2017-10-23

Applicant: Micron Technology, Inc.

Inventor： Angelo Della Monica ,  Eric Kwok Fung Yuen ,  Pasquale Cimmino ,  Massimo Iaculo ,  Francesco Falanga

IPC: G06F3/06

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which functionalities of a memory device of the apparatus can be extended by changing data flow behaviour associated with standard commands used between a host platform and the memory device. Such functionalities can include debug capabilities. In an embodiment, a standard write command and data using a standard protocol to write to a memory device is received in the memory device, where the data is setup information to enable an extension component in the memory device. An extension component includes instructions in the memory device to execute operations on components of the memory device. The memory device can execute operations of the enabled extension component in the memory device based on the setup information. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20190220192A1

公开(公告)日：2019-07-18

申请号：US16361445

申请日：2019-03-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Francesco Falanga ,  Danilo Caraccio

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0246 ,  G06F2212/7211

Abstract: Methods for automatically performing a background operation in a memory device might include automatically performing the background operation responsive to automatic performance of the background operation being enabled and receiving a start command.

公开(公告)号：US20160231932A1

公开(公告)日：2016-08-11

申请号：US15131447

申请日：2016-04-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Francesco Falanga ,  Danilo Caraccio

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0246 ,  G06F2212/7211

Abstract: A host that is coupled to a memory device is configured to read a status register of the memory device to determine if the memory device supports host controlled enablement of automatic background operations. The memory device responds to the host regarding whether the memory device supports host controlled enablement of automatic background operations. The host can enable the automatic background operations if the memory device supports this feature. The host can then set a time period in the memory device that is indicative of when the memory device can automatically perform the background operations.

Abstract translation: 耦合到存储设备的主机被配置为读取存储器设备的状态寄存器以确定存储器设备是否支持主机控制的自动后台操作的启用。 存储器设备响应于主机是否支持主机控制启用自动后台操作。 如果内存设备支持此功能，主机可以启用自动后台操作。 然后，主机可以在存储器设备中设置指示存储器设备何时可以自动执行后台操作的时间段。

公开(公告)号：US20140201473A1

公开(公告)日：2014-07-17

申请号：US13739453

申请日：2013-01-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Francesco Falanga ,  Danilo Caraccio

IPC: G06F12/00

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0246 ,  G06F2212/7211

Abstract: A host that is coupled to a memory device is configured to read a status register of the memory device to determine if the memory device supports host controlled enablement of automatic background operations. The memory device responds to the host regarding whether the memory device supports host controlled enablement of automatic background operations. The host can enable the automatic background operations if the memory device supports this feature. The host can then set a time period in the memory device that is indicative of when the memory device can automatically perform the background operations.

Abstract translation: 耦合到存储设备的主机被配置为读取存储器设备的状态寄存器以确定存储器设备是否支持主机控制的自动后台操作的启用。 存储器设备响应于主机是否支持主机控制启用自动后台操作。 如果内存设备支持此功能，主机可以启用自动后台操作。 然后，主机可以在存储器设备中设置指示存储器设备何时可以自动执行后台操作的时间段。