公开(公告)号：US20230334002A1

公开(公告)日：2023-10-19

申请号：US18309102

申请日：2023-04-28

Applicant: Micron Technology, Inc.

Inventor： Christopher Joseph Bueb ,  Poorna Kale

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4027 ,  G06F13/1605

Abstract: A solid state drive having a drive aggregator and multiple component solid state drives. Different component solid state drives in solid state drive are configured with different optimizations of memory/storage operations. An address map in the solid state drive is used by the drive aggregator to host different namespaces in the component solid state drives based on optimization requirements of the namespaces and based on the optimizations of memory operations that have been implement in the component solid state drives.

公开(公告)号：US11741710B2

公开(公告)日：2023-08-29

申请号：US17077981

申请日：2020-10-22

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale

IPC: G06V20/40 ,  G06N3/08

CPC classification number: G06V20/40 ,  G06N3/08

Abstract: Systems, devices, and methods related to video analysis using an Artificial Neural Network (ANN) are described. For example, a data storage device can be configured to perform the computation of an ANN to recognize or classify features captured in the video images. The recognition or classification results of a prior video frame can be used to accelerate the analysis of the next video frame. The ANN can be organized in layers, where the intermediate result of a current layer can be further analyzed by a next layer for improved accuracy and confidence level. Before or while processing using the next layer, the intermediate result can be compared to the results obtained for the prior frame. If, in view of the results of the prior frame, the confidence level of the intermediate result is boosted to above a threshold, the subsequent layer(s) can be skipped or terminated early.

公开(公告)号：US20230266918A1

公开(公告)日：2023-08-24

申请号：US17652412

申请日：2022-02-24

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0629 ,  G06F3/0604 ,  G06F3/0673

Abstract: Methods, systems, and devices for techniques to season memory cells are described. A memory device may receive a command to season the memory device from a device configured to season the memory device or from a host device. Based on receiving the command, the memory device may identify a quantity of cycles to season the memory device based on receiving the command. In one case, the memory device may identify the quantity of cycles based on the command including an indication of the quantity of cycles used to season the memory device. In another case, the memory device may identify the quantity of cycles based on the command including one or more parameters associated with operating the memory device. In either case, the memory device may execute the quantity of cycles and indicate a completion of seasoning the memory device based on executing the quantity of cycles.

公开(公告)号：US11733763B2

公开(公告)日：2023-08-22

申请号：US16987127

申请日：2020-08-06

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3234 ,  G06F1/3296 ,  G06F1/3287 ,  G06F1/3228 ,  G06F17/16 ,  G06N3/08 ,  G06F9/50 ,  G06F9/30 ,  G06N3/063

CPC classification number: G06F1/3275 ,  G06F1/3228 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3001 ,  G06F9/5027 ,  G06F17/16 ,  G06N3/063 ,  G06N3/08

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory that includes multiple memory groups having independent power modes. The random access memory is configured to store data representative of parameters of an Artificial Neural Network and representative of instructions executable by the Deep Learning Accelerator to perform matrix computation to generate an output of the Artificial Neural Network. During execution of the instructions, a power manager may adjust grouping of memory addresses mapped into the memory groups and adjust power modes of the memory groups to reduce power consumption and to avoid performance impact.

公开(公告)号：US20230253024A1

公开(公告)日：2023-08-10

申请号：US17668197

申请日：2022-02-09

Applicant: Micron Technology, Inc.

Inventor： Qi Dong ,  Poorna Kale

IPC: G11C11/406 ,  G06F11/07

CPC classification number: G11C11/40611 ,  G11C11/40622 ,  G06F11/076 ,  G06F11/0772 ,  G11C2211/4061

Abstract: Methods, systems, and devices for techniques for memory system refresh are described. In some cases, a memory system may prioritize refreshing blocks of memory cells containing control information for the file system of the memory system. For example, the memory system may identify a block of memory cells containing control information and adjust an error threshold for refreshing the blocks of memory cells to be lower than an error threshold for refreshing the blocks of memory cells containing data other than control information. Additionally or alternatively, the memory system may perform a refresh control operation for the block of memory cells with a higher frequency (e.g., more frequently) than for other blocks of memory cells.

公开(公告)号：US11694076B2

公开(公告)日：2023-07-04

申请号：US16601381

申请日：2019-10-14

Applicant: Micron Technology, Inc.

Inventor： Amit Gattani ,  Poorna Kale

IPC: G05B13/02 ,  G06G7/00 ,  G06E1/00 ,  G06N3/08 ,  G06N3/04 ,  G06F13/16

CPC classification number: G06N3/08 ,  G06F13/1668 ,  G06N3/04

Abstract: A memory component can include memory cells where a first region of the memory cells is to store a machine learning model and a second region of the memory cells is to store input data and output data of a machine learning operation. A controller can be coupled to the memory component with one more internal buses to perform the machine learning operation by applying the machine learning model to the input data to generate the output data.

公开(公告)号：US11693562B2

公开(公告)日：2023-07-04

申请号：US16562230

申请日：2019-09-05

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Robert Richard Noel Bielby

IPC: G06F3/06 ,  G06N3/08 ,  G06N3/049 ,  G06N3/045

CPC classification number: G06F3/0613 ,  G06F3/067 ,  G06F3/0653 ,  G06N3/045 ,  G06N3/049 ,  G06N3/08

Abstract: Systems, methods and apparatus of intelligent bandwidth allocation to different types of operations to access storage media in a data storage device. For example, a data storage device of a vehicle includes: storage media components; a controller configured to store data into and retrieve data from the storage media components according to commands received in the data storage device; and an artificial neural network configured to receive, as input and as a function of time, operating parameters indicative a data access pattern, and generate, based on the input, a prediction to determine an optimized bandwidth allocation scheme for controlling access by different types of operations in the data storage device to the storage media components. The controller is configured to schedule the operations of the different types to access the one or more storage media components according to the optimized bandwidth allocation scheme.

公开(公告)号：US11676010B2

公开(公告)日：2023-06-13

申请号：US16601392

申请日：2019-10-14

Applicant: Micron Technology, Inc.

Inventor： Amit Gattani ,  Poorna Kale

IPC: G05B13/02 ,  G06F1/00 ,  G06F7/00 ,  G06N3/08 ,  G06F13/16

CPC classification number: G06N3/08 ,  G06F13/1668

Abstract: A system includes a memory component to store host data from a host system and to store a machine learning model and input data. A controller includes an in-memory logic to perform a machine learning operation by applying the machine learning model to the input data to generate an output data. A bus can receive additional host data from the host system and provide the additional host data to the memory component. An additional bus can receive machine learning data from the host system and provide the machine learning data to the in-memory logic that is to perform the machine learning operation.

公开(公告)号：US11668797B2

公开(公告)日：2023-06-06

申请号：US16719196

申请日：2019-12-18

Applicant: Micron Technology, Inc.

Inventor： Anakha Vasanthakumaribabu ,  Poorna Kale ,  Robert Richard Noel Bielby

IPC: G01S7/41 ,  G06N5/04 ,  G01S13/931 ,  G01S13/89

CPC classification number: G01S7/417 ,  G01S13/89 ,  G01S13/931 ,  G06N5/04 ,  G01S2013/9318 ,  G01S2013/9319 ,  G01S2013/93185

Abstract: Systems, methods and apparatuses of radar Electronic Control Units (ECUs) of autonomous vehicles. A radar ECU can include: a memory configured to store a radar image and an Artificial Neural Network (ANN); an inference engine configured to use the (ANN) to analyze the radar image and generate inference results; and a communication interface coupled to a computer system of a vehicle to implement an advanced driver assistance system to operate the controls according to the inference results and a sensor data stream generated by sensors configured on the vehicle.

公开(公告)号：US11650746B2

公开(公告)日：2023-05-16

申请号：US16562222

申请日：2019-09-05

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Robert Richard Noel Bielby

IPC: G06F3/06 ,  G06F12/02 ,  G06N3/049 ,  G05D1/00 ,  G05D1/02

CPC classification number: G06F3/0638 ,  G05D1/0022 ,  G05D1/0088 ,  G05D1/0274 ,  G06F3/0616 ,  G06F3/0673 ,  G06F12/0269 ,  G06N3/049

Abstract: Systems, methods and apparatus of intelligent write-amplification reduction for data storage devices configured on autonomous vehicles. For example, a data storage device of a vehicle includes: one or more storage media components; a controller configured to store data into and retrieve data from the one or more storage media components according to commands received in the data storage device; an address map configured to map between: logical addresses specified in the commands received in the data storage device, and physical addresses of memory cells in the one or more storage media components; and an artificial neural network configured to receive, as input and as a function of time, operating parameters indicative a data access pattern, and generate, based on the input, a prediction to determine an optimized data placement scheme. The controller is configured to adjust the address map according to the optimized data placement scheme.