公开(公告)号：US11720489B2

公开(公告)日：2023-08-08

申请号：US17902384

申请日：2022-09-02

Applicant: Micron Technology, Inc.

Inventor： Xinghui Duan ,  Giuseppe D'Eliseo ,  Lalla Fatima Drissi ,  Giuseppe Ferrari ,  Eric Kwok Fung Yuen ,  Massimo Iaculo

IPC: G06F12/02 ,  G06F12/1009

CPC classification number: G06F12/0253 ,  G06F12/1009 ,  G06F2212/1044 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which storage in the memory device is managed. An allocation can include conducting a garbage collection procedure to free up one or more blocks. In various embodiments, execution of a garbage collection procedure can be based on operation of two tables with respect to a logical to physical mapping table split into logical to physical mapping table regions saved in the memory device. The first table can maintain counts of valid pages in blocks for a logical to physical mapping table region. The second table can include bits to identify logical to physical mapping table regions involved in the garbage collection procedure based on the entries in the first table. Search of the second table can determine logical to physical mapping table regions involved in the garbage collection. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20220300409A1

公开(公告)日：2022-09-22

申请号：US17272113

申请日：2020-09-21

Applicant: Micron Technology, Inc.

Inventor： Xinghui Duan ,  Bin Zhao ,  Jianxiong Huang

IPC: G06F12/02 ,  G06F12/06 ,  G06F13/16

Abstract: Devices and techniques for improving memory access operations of a memory device are provided. In an example, a method can include loading multiple LBA-to-physical address (L2P) regions of an L2P table from memory arrays of the memory device to a mapping cache in response to determining the LBA of the memory access command is not within the L2P region including of a mapping cache. When the memory access command is a sequential command, the multiple L2P regions loaded to the mapping cache can provide improved memory access performance.

公开(公告)号：US11409462B2

公开(公告)日：2022-08-09

申请号：US16959064

申请日：2019-12-31

Applicant: Micron Technology, Inc.

Inventor： Huachen Li ,  Xu Zhang ,  Zhong Xian Li ,  Xinghui Duan ,  Xing Wang ,  Tian Liang

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0882

Abstract: Devices and techniques for data removal marking in a memory device are described herein. A delete command can be received at the memory device. A count of data portions in the delete command can be compared to determine whether the count is below a threshold. In response to determining that the count of data portions is below the threshold, the data portions can be written to a buffer. When a buffer full event is detected, a segment of an L2P data structure can be loaded into working memory of the memory device. Then, each record in the segment of the L2P data structure that has a corresponding entry in the buffer can be updated to mark the data as removable (e.g., invalid).

公开(公告)号：US20220188018A1

公开(公告)日：2022-06-16

申请号：US17688304

申请日：2022-03-07

Applicant: Micron Technology, Inc.

Inventor： Eric Kwok Fung Yuen ,  Giuseppe Ferrari ,  Massimo Iaculo ,  Lalla Fatima Drissi ,  Xinghui Duan ,  Giuseppe D'Eliseo

IPC: G06F3/06 ,  G06F12/02

Abstract: Devices and techniques for NAND logical-to-physical table region tracking are described herein. A write request, including a logical page and data to be written at the logical page, is received at a controller of a NAND device. The NAND controller may then establish an entry in a logical-to-physical (L2P) mapping table between the logical page and a physical page of a physical block of the NAND device to which the data is written. Here, the entry may be in a region of the L2P mapping table that is one of multiple regions. An indication of the region may be written in a data structure corresponding to the physical block.

公开(公告)号：US20210141557A1

公开(公告)日：2021-05-13

申请号：US16075464

申请日：2017-12-21

Applicant: MICRON TECHNOLOGY INC.

Inventor： Eric Kwok Fung Yuen ,  Giuseppe Ferrari ,  Massimo Iaculo ,  Lalla Fatima Drissi ,  Xinghui Duan ,  Giuseppe D'Eliseo

IPC: G06F3/06

Abstract: Devices and techniques for NAND logical-to-physical table region tracking are described herein. A write request, including a logical page and data to be written at the logical page, is received at a controller of a NAND device. The NAND controller may then establish an entry in a logical-to-physical (L2P) mapping table between the logical page and a physical page of a physical block of the NAND device to which the data is written. Here, the entry may be in a region of the L2P mapping table that is one of multiple regions. An indication of the region may be written in a data structure corresponding to the physical block.

公开(公告)号：US10725904B2

公开(公告)日：2020-07-28

申请号：US16075543

申请日：2017-12-13

Applicant: Micron Technology, Inc.

Inventor： Zhao Cui ,  Eric Kwok Fung Yuen ,  Guan Zhong Wang ,  Xinghui Duan ,  Giuseppe D'Eliseo ,  Giuseppe Ferrari

IPC: G06F12/02 ,  G06F12/0873

Abstract: Devices and techniques for synchronizing NAND logical-to-physical table region tracking are described herein. Table region data structures for physical blocks are maintained. These structures include logical-to-physical (L2P) mapping table portions that point to the respective physical blocks. When garbage collection is performed on a block, table region structures for that block, and another (e.g., the next block to be garbage collected) are read to avoid loading L2P table regions that do not point to the block. If any of the read portions of the L2P table region fail to point to either the block or the other block, these L2P table portions are removed from the loaded table region data structures.

公开(公告)号：US11922012B2

公开(公告)日：2024-03-05

申请号：US17626713

申请日：2019-09-10

Applicant: Micron Technology, Inc.

Inventor： Xinghui Duan

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/064 ,  G06F3/0688

Abstract: Apparatus and methods are disclosed, including a sequential mapping table located within a flash memory array of a flash memory device. Selected examples include firmware in the flash memory device to load the sequential mapping table into a cache upon power and perform read and write operations using the sequential mapping table. Selected examples include firmware in the flash memory device to store an updated sequential mapping table into the flash memory array upon power down of the flash memory device.

公开(公告)号：US11740819B2

公开(公告)日：2023-08-29

申请号：US17486420

申请日：2021-09-27

Applicant: Micron Technology, Inc.

Inventor： Zhao Cui ,  Eric Kwok Fung Yuen ,  Guan Zhong Wang ,  Xinghui Duan ,  Hua Chen Li

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201

Abstract: Devices and techniques for variable width superblock addressing are described herein. A superblock width, specified in number of planes, is obtained. A superblock entry is created in a translation table of a NAND device. Here, the superblock entry may include a set of blocks, from the NAND device, that have the same block indexes across multiple die of the NAND device. The number of unique block indexes are equal to the number of planes and in different planes. A request, received from a requesting entity, is performed using the superblock entry. Performing the request includes providing a single instruction to multiple die of the NAND device and multiple data segments. Here, a data segment corresponds to a block in the set of blocks specified by a tuple of block index and die. A result of the request is then returned to the requesting entity.

公开(公告)号：US11720278B2

公开(公告)日：2023-08-08

申请号：US17869262

申请日：2022-07-20

Applicant: Micron Technology, Inc.

Inventor： Huachen Li ,  Xu Zhang ,  Zhong Xian Li ,  Xinghui Duan ,  Xing Wang ,  Tian Liang

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0882

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0882 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7209

Abstract: Devices and techniques for data removal marking in a memory device are described herein. A delete command can be received at the memory device. A count of data portions in the delete command can be compared to determine whether the count is below a threshold. In response to determining that the count of data portions is below the threshold, the data portions can be written to a buffer. When a buffer full event is detected, a segment of an L2P data structure can be loaded into working memory of the memory device. Then, each record in the segment of the L2P data structure that has a corresponding entry in the buffer can be updated to mark the data as removable (e.g., invalid).

公开(公告)号：US20220414003A1

公开(公告)日：2022-12-29

申请号：US17902384

申请日：2022-09-02

Applicant: Micron Technology, Inc.

Inventor： Xinghui Duan ,  Giuseppe D'Eliseo ,  Lalla Fatima Drissi ,  Giuseppe Ferrari ,  Eric Kwok Fung Yuen ,  Massimo Iaculo

IPC: G06F12/02 ,  G06F12/1009

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which storage in the memory device is managed. An allocation can include conducting a garbage collection procedure to free up one or more blocks. In various embodiments, execution of a garbage collection procedure can be based on operation of two tables with respect to a logical to physical mapping table split into logical to physical mapping table regions saved in the memory device. The first table can maintain counts of valid pages in blocks for a logical to physical mapping table region. The second table can include bits to identify logical to physical mapping table regions involved in the garbage collection procedure based on the entries in the first table. Search of the second table can determine logical to physical mapping table regions involved in the garbage collection. Additional apparatus, systems, and methods are disclosed.