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    OPEN TRANSLATION UNIT MANAGEMENT USING AN ADAPTIVE READ THRESHOLD
    21.
    发明公开
    OPEN TRANSLATION UNIT MANAGEMENT USING AN ADAPTIVE READ THRESHOLD 审中-公开

    公开(公告)号：US20230186959A1

    公开(公告)日：2023-06-15

    申请号：US17546431

    申请日：2021-12-09

    Applicant: Micron Technology, Inc.

    Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Zhongguang Xu ,  Jiangli Zhu

    IPC: G11C7/10

    CPC classification number: G11C7/1063

    Abstract: A first read operation is performed on a first set of memory cells addressable by a first wordline (WL), and a second read operation is performed on a second set of memory cells addressable by a second WL, wherein the first set of memory cells and the second set of memory cells are comprised by an open TU of memory cells. A first threshold voltage offset bin associated with the first WL is identified. A second threshold voltage offset bin associated with the second WL is identified. Respective threshold voltage offset bins for each WL of a plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on at least one of the first threshold voltage offset bin and the second threshold voltage offset bin. Respective default threshold voltages for each WL of the plurality of WLs are updated based on the threshold voltage offset bins.

    ADAPTIVE FREQUENCY CONTROL FOR HIGH-SPEED MEMORY DEVICES
    24.
    发明申请
    ADAPTIVE FREQUENCY CONTROL FOR HIGH-SPEED MEMORY DEVICES 有权

    公开(公告)号：US20220058070A1

    公开(公告)日：2022-02-24

    申请号：US16996267

    申请日：2020-08-18

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Jian HUANG ,  Zhenming ZHOU ,  Zhongguang Xu ,  Murong Lang

    IPC: G06F11/07 ,  G06F11/10 ,  G11C16/26

    Abstract: A command to read specific data stored at a memory die is received. A read operation is performed while operating both a memory controller and the memory die simultaneously at a first frequency. A processor determines whether a first error rate associated with the memory die satisfies a first error threshold criterion (e.g., UECC). Responsive to determining that the first error rate satisfies the first error threshold criterion, the read operation is repeated while operating at least one of the memory controller or the memory die at a second frequency that is different from the first frequency. The processor determines whether a second error rate associated with the memory die satisfies a second error threshold criterion. Responsive to determining that the second error rate satisfies the second error threshold criterion (e.g. UECC persists), determining that the read operation has failed.

    Reliability health prediction by high-stress seasoning of memory devices
    26.
    发明授权
    Reliability health prediction by high-stress seasoning of memory devices 有权

    公开(公告)号：US11238950B1

    公开(公告)日：2022-02-01

    申请号：US16925222

    申请日：2020-07-09

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Zhongguang Xu ,  Murong Lang ,  Zhenming Zhou

    IPC: G11C29/10 ,  G01R31/311 ,  G11C29/52 ,  G11C29/04

    Abstract: An accelerated seasoning cycle criterion is associated with a memory die of a number of memory dies. The memory die is subjected to one or more accelerated seasoning conditions during accelerated seasoning cycles. Responsive to determining that the accelerated seasoning cycle criterion has been satisfied, a defect scan is performed on the memory die. The memory die is associated with a respective reliability bin of a plurality of reliability bins in view of a result of the defect scan, wherein the result of the defect scan satisfies one or more predetermined threshold reliability criteria corresponding to the respective reliability bin.

    OPERATIONS ON PARTIALLY PROGRAMMED ERASE BLOCKS
    28.
    发明申请
    OPERATIONS ON PARTIALLY PROGRAMMED ERASE BLOCKS 有权

    公开(公告)号：US20250140320A1

    公开(公告)日：2025-05-01

    申请号：US18784434

    申请日：2024-07-25

    Applicant: Micron Technology, Inc.

    Inventor： Hanping Chen ,  Zhongguang Xu ,  Murong Lang ,  Zhenming Zhou

    IPC: G11C16/14 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34

    Abstract: Apparatuses and methods for performing sensing operations on partially programmed erase blocks are provided. One example apparatus can include a memory array comprising a plurality of erase blocks and a controller coupled to the memory array. The controller can be configured to apply a first sensing voltage to a first access line of a first group of access lines corresponding to the first erase block during a first sensing operation on the first erase block that is partially programmed, apply a first pass voltage to a number of programmed access lines of the first group of access lines corresponding to the first erase block during the first sensing operation, and apply a second pass voltage a number of unprogrammed access lines of the first group of access lines corresponding to the first erase block during the first sensing operation.

    INVERSE ERASE FOR MEMORY COMPONENTS
    29.
    发明公开
    INVERSE ERASE FOR MEMORY COMPONENTS 审中-公开

    公开(公告)号：US20240361945A1

    公开(公告)日：2024-10-31

    申请号：US18645713

    申请日：2024-04-25

    Applicant: Micron Technology, Inc.

    Inventor： Zhongguang Xu ,  Ronit Roneel Prakash

    IPC: G06F3/06

    CPC classification number: G06F3/0652 ,  G06F3/0604 ,  G06F3/0679

    Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to efficiently erase memory blocks. The controller receives a request to erase an individual memory component of a set of memory components. The controller applies an erase pulse to the individual memory component in response to the request. The controller, following application of the erase pulse, applies a pre-program pulse to the individual memory component.

    SELECT GATE MAINTENANCE WITH ADAPTIVE SCAN FREQUENCY IN A MEMORY SUB-SYSTEM
    30.
    发明公开
    SELECT GATE MAINTENANCE WITH ADAPTIVE SCAN FREQUENCY IN A MEMORY SUB-SYSTEM 审中-公开

    公开(公告)号：US20240153570A1

    公开(公告)日：2024-05-09

    申请号：US18384716

    申请日：2023-10-27

    Applicant: Micron Technology, Inc.

    Inventor： Zhongguang Xu ,  Murong Lang

    IPC: G11C16/34 ,  G11C16/26

    CPC classification number: G11C16/3495 ,  G11C16/26 ,  G11C16/3404

    Abstract: A processing device, operatively coupled with a memory device, determines a number of program/erase cycles performed on a block of the memory device. The processing device determines that the number of program/erase cycles performed on the block satisfies a first threshold criterion, wherein the first threshold criterion corresponds to a frequency interval for performing a threshold voltage integrity scan on the block. The processing device performs a threshold voltage integrity scan on the block to determine an error count associated with a current threshold voltage of at least one select gate device of the block. Responsive to the error count associated with the current threshold voltage of the at least one select gate device satisfying a second threshold criterion, the processing device determines a rate of change associated with the current threshold voltage of the at least one select gate device. The processing device updates, based on the rate of change, the frequency interval for performing a threshold voltage integrity scan on the block.

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