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21.发明授权High-precision analog reading circuit for flash analog memory arrays using negative feedback 失效用于闪存模拟存储器阵列的高精度模拟读取电路使用负反馈
公开(公告)号：US6016272A
公开(公告)日：2000-01-18
申请号：US60165
申请日：1998-04-14
CPC分类号： G11C16/28 , G11C27/005
摘要： An analog reading circuit having a current mirror circuit forcing two identical currents into a cell to be read and into a reference cell. An operational amplifier has an inverting input connected to the drain terminal of the cell to be read, a non-inverting input connected to the drain terminal of the reference cell, and an output connected to the gate terminal of the reference cell. The reference cell therefore forms part of a negative feedback loop which maintains the overdrive voltages of the cell to be read and the reference cell constant, irrespective of temperature variations. The reading circuit is also of high precision and has a high reading speed.
摘要翻译： 一种具有电流镜像电路的模拟读取电路，其将两个相同的电流强制进入待读取的单元并进入参考单元。 运算放大器具有连接到要读取的单元的漏极端子的反相输入端，连接到参考单元的漏极端子的非反相输入端和连接到参考单元栅极端子的输出端。 因此，参考单元形成负反馈回路的一部分，其保持要读取的单元的过驱动电压和参考单元恒定，而与温度变化无关。 读取电路也具有高精度，读取速度快。
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22.发明授权Circuit and method of reading cells of an analog memory array, in particular of the flash type 失效读取模拟存储器阵列的单元的电路和方法，特别是闪存类型
公开(公告)号：US5973959A
公开(公告)日：1999-10-26
申请号：US121024
申请日：1998-07-22
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5642 , G11C16/26 , G11C2211/5645 , G11C27/02
摘要： A reading circuit comprises a current mirror circuit connected, at a first and a second output node, to the drain terminals of an array cell and of a reference cell; a comparator whose inputs are connected to the output nodes of the current mirror circuit; a ramp generator having an enabling input connected to the output of the comparator and an output connected to the control terminal of the reference cell. Biasing the gate terminal of the array cell to a constant voltage, when the currents flowing in the array cell and in the reference cell are equal, the value assumed by the ramp voltage is proportional to the threshold value of the array cell; at that time the comparator is triggered and discontinues the ramp increase, supplying as output the desired threshold value.
摘要翻译： 读取电路包括在第一和第二输出节点处连接到阵列单元和参考单元的漏极端子的电流镜电路; 比较器，其输入端连接到电流镜电路的输出节点; 斜坡发生器，其具有连接到比较器的输出的使能输入和连接到参考单元的控制端的输出。 当阵列单元和参考单元中流动的电流相等时，将阵列单元的栅极端子偏置为恒定电压，斜坡电压所假定的值与阵列单元的阈值成比例; 此时比较器被触发并停止斜坡增加，作为输出提供所需的阈值。
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23.发明授权Method and device for analog programming of flash EEPROM memory cells with autoverify 有权用于自动验证的闪存EEPROM存储单元的模拟编程方法和设备
公开(公告)号：US6081448A
公开(公告)日：2000-06-27
申请号：US162639
申请日：1998-09-28
CPC分类号： G11C27/005
摘要： A device for analog programming is disclosed. The device comprises a current mirror circuit connected to drain terminals of a cell to be programmed and of a MOS reference transistor. An operational amplifier has inputs connected to the drain terminals of the cell and respectively of the MOS transistor and an output connected to the control terminal of the MOS transistor. During programming, the control and drain terminals of the cell are biased at corresponding programming voltages and the output voltage of the operational amplifier, which is correlated to the current threshold voltage level of the cell, is monitored and the programming is interrupted when this output voltage becomes at least equal to a reference voltage correlated to the threshold value desired for the cell.
摘要翻译： 公开了一种用于模拟编程的装置。 该器件包括连接到要编程的单元的漏极端子和MOS参考晶体管的电流镜电路。 运算放大器具有连接到单元的漏极端子和MOS晶体管的漏极端子和连接到MOS晶体管的控制端子的输出的输入。 在编程期间，单元的控制和漏极端子以相应的编程电压被偏置，并且监视与电池的当前阈值电压电平相关的运算放大器的输出电压，并且当该输出电压 变得至少等于与小区所需的阈值相关的参考电压。
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24.发明授权公开(公告)号：US06195283B1
公开(公告)日：2001-02-27
申请号：US09076013
申请日：1998-05-11
IPC分类号： G11C700
CPC分类号： G11C27/005
摘要： For each memory cell to be programmed, the present threshold value of the cell is determined; the desired threshold value is acquired; the analog distance between the present threshold value and the desired threshold value is calculated; and a programming pulse is then generated, the duration of which is proportional to the analog distance calculated. The programming and reading cycle is repeated until the desired threshold is reached. By this means a time saving is obtained, owing to the reduction of the number of intermediate reading steps. The method permits programming in parallel and simultaneously of a plurality of cells of a memory array which is connected to a single word line and to different bit lines, each with a programming pulse the duration of which is proportional to the analog distance calculated for the same cell. The programming process is thus very fast, owing to parallel application of the programming and the saving in the intermediate reading cycles.
摘要翻译： 对于要编程的每个存储器单元，确定单元的当前阈值; 获取期望的阈值; 计算当前阈值与期望阈值之间的模拟距离; 然后产生编程脉冲，其持续时间与计算出的模拟距离成比例。 重复编程和读取周期，直到达到所需的阈值。 由于中间读取步骤数量的减少，可以节省时间。 该方法允许并行地编程存储器阵列的多个单元，其连接到单个字线和不同的位线，每个存储器阵列的编程脉冲的持续时间与为同一个字线计算的模拟距离成比例 细胞。 编程过程非常快，因为编程的并行应用和中间阅读周期的节省。
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25.发明授权公开(公告)号：US06169691A
公开(公告)日：2001-01-02
申请号：US09397387
申请日：1999-09-15
申请人： Marco Pasotti , Frank Lhermet , Pier Luigi Rolandi
发明人： Marco Pasotti , Frank Lhermet , Pier Luigi Rolandi
IPC分类号： G11C1606
CPC分类号： G11C16/3431 , G11C11/5621 , G11C16/3418
摘要： A method for restoring the charge lost from memory cells, such as to restore the original voltage levels, within a time equivalent to the retention time. The condition of the memory cell is determined, for example, when the memory is switched on, or based on the time elapsed since the previous programming/restoration, or based on the difference between the present threshold voltage of the reference cells and the original threshold voltage of the (suitably stored) reference cells, or when predetermined operating conditions occur. This makes it possible to prolong the life of nonvolatile memories, in particular of multilevel type, wherein the retention time decreases as the number of levels (bits/cell) is increased.
摘要翻译： 一种用于在等同于保留时间的时间内恢复从存储器单元丢失的电荷，例如恢复原始电压电平的方法。 确定存储器单元的状态，例如，当存储器被接通时，或者基于从先前的编程/恢复以来所经过的时间，或者基于参考单元的当前阈值电压与原始阈值之间的差 （适当存储的）参考单元的电压，或者当发生预定操作条件时。 这使得可以延长非易失性存储器的使用寿命，特别是延长多级电路的寿命，其中保持时间随着电平数（位/电池）的增加而减少。
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公开(公告)号：US06581134B2
公开(公告)日：2003-06-17
申请号：US09817804
申请日：2001-03-26
IPC分类号： G06F1200
CPC分类号： G06F12/0246 , G06F2212/7203 , G06F2212/7211
摘要： A FLASH memory is organized in a plurality of physical sectors which may be split into a plurality of singularly addressable logic sectors. Each logic sector may include a memory space of a predetermined size and a chain pointer assuming a neutral value or a value pointing to a second logic sector associated with a respective chain pointer at the neutral value. Each logic sector may also include a status indicator assuming at least one of a first value if the logic sector is empty, a second value if the data therein belongs to the logic sector, a third value if the data does not belong to the logic sector, and a fourth value if the data has been erased. Further, each logic sector may include a remap pointer assuming the neutral value or a value pointing directly or indirectly to the chain pointer of a third logic sector.
摘要翻译： FLASH存储器被组织在多个物理扇区中，这些扇区可以被分成多个可单独寻址的逻辑扇区。 每个逻辑扇区可以包括预定大小的存储器空间和假定中性值的链指针或指向与中性值处的相应链指针相关联的第二逻辑扇区的值。 如果逻辑扇区为空，则每个逻辑扇区还可以包括状态指示符，如果其中的数据属于逻辑扇区，则假设第二值为第一值;如果数据不属于逻辑扇区，则第三值 ，如果数据已被擦除，则为第四个值。 此外，每个逻辑扇区可以包括假定中性值的重映射指针或直接或间接指向第三逻辑扇区的链指针的值。
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27.发明授权Embeddable flash memory system for non-volatile storage of code, data and bit-streams for embedded FPGA configurations 有权可嵌入式闪存系统，用于非易失性存储用于嵌入式FPGA配置的代码，数据和位流公开(公告)号：US07251705B2
公开(公告)日：2007-07-31
申请号：US10768743
申请日：2004-01-29
IPC分类号： G06F12/00
CPC分类号： G11C16/30
摘要： An application-specific embeddable flash memory having three content-specific I/O ports and delivering a peak read throughput of 1.2 GB/s. The memory is combined with a special automatic programming gate voltage ramp generator circuit having a programming rate of 1 Mbyte/s for non-volatile storage of code, data, and embedded FPGA bit stream configurations. The test chip uses a NOR-type 0.18 μm flash embedded technology with 1.8V power supply, two poly, six metal and memory cell size of 0.35 μm2.
摘要翻译： 具有三个特定于内容的I / O端口并具有1.2 GB / s的峰值读取吞吐量的特定于应用的嵌入式闪存。 该存储器与用于代码，数据和嵌入式FPGA位流配置的非易失性存储的具有1兆字节/秒的编程速率的专用自动编程门电压斜坡发生器电路组合。 测试芯片采用NOR型0.18 mum闪存嵌入式技术，具有1.8V电源，两个聚六金属和存储单元尺寸为0.35 mum 2。
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公开(公告)号：US06667903B2
公开(公告)日：2003-12-23
申请号：US10017502
申请日：2001-12-14
申请人： Guido De Sandre , Marco Pasotti , Pier Luigi Rolandi , Giovani Guaitini , David Iezzi , Marco Poles
发明人： Guido De Sandre , Marco Pasotti , Pier Luigi Rolandi , Giovani Guaitini , David Iezzi , Marco Poles
IPC分类号： G11C1604
CPC分类号： G11C11/5628 , G11C11/5621 , G11C11/5635 , G11C17/146
摘要： It is described a programming method for a multilevel memory cell able to store a plurality of bits in a plurality of levels. The method comprises the phases of: initially programming a cell threshold value to a first set of levels [0;(m−1)] being m a submultiple of the plurality of levels of the multilevel cell; reprogramming without erasing another set of levels [m;(2m−1)] containing the same number m of levels as the first set; reiterating the reprogramming without erasing phase until the levels of the multilevel cell are exhausted. It is also described a multilevel memory device of the type comprising a plurality of multilevel memory cells organized into sectors, the sectors being themselves split into a plurality of data units wherein a data updating operation is performed in parallel, the data units being programmed by means of the programming method.
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29.发明授权Method for controlled soft programming of non-volatile memory cells, in particular of the flash EEPROM and EPROM type 有权用于非易失性存储单元的受控软编程的方法，特别是闪存EEPROM和EPROM类型的方法公开(公告)号：US06381177B1
公开(公告)日：2002-04-30
申请号：US09699309
申请日：2000-10-27
IPC分类号： G11C1600
CPC分类号： G11C16/12
摘要： A method for controlled soft programming of a plurality of non-volatile memory cells, having bulk terminals connected to one another and to a common bulk line. The method includes supplying at least one soft programming pulse to the plurality of memory cells for a time interval. In this step, a bulk voltage with a rising negative ramp is applied to the common bulk line for the time interval. By this means, the threshold voltage of the cells is increased by body effect, and initially only the most depleted cells are soft programmed, with a limited drain current. Subsequently, when the bulk voltage increases, the cells with a higher threshold voltage are also soft programmed, until all the cells have reached the required minimum threshold value.
摘要翻译： 一种用于多个非易失性存储器单元的受控软编程的方法，其具有彼此连接的批量端子和公共批量线。 该方法包括在一段时间间隔内向多个存储器单元提供至少一个软编程脉冲。 在该步骤中，具有上升负斜率的体电压在时间间隔上被施加到公共批量线。 通过这种方式，电池的阈值电压由于体效应而增加，并且最初只有最耗尽的电池被软编程，具有有限的漏极电流。 随后，当体电压增加时，具有较高阈值电压的单元也被软编程，直到所有单元达到所需的最小阈值。
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30.发明授权公开(公告)号：US07360068B2
公开(公告)日：2008-04-15
申请号：US10768401
申请日：2004-01-30
IPC分类号： G06F13/00
CPC分类号： G06F15/7867 , G11C16/30 , Y02D10/12 , Y02D10/13
摘要： A dynamically reconfigurable processing unit includes a microprocessor, and an embedded Flash memory for non-volatile storage of code, data and bit-streams. The embedded Flash includes a field programmable gate array (FPGA) port. The reconfigurable processing unit further includes a direct memory access (DMA) channel, and an S-RAM embedded FPGA for FPGA reconfigurations. The S-RAM embedded FPGA has an FPGA programming interface connected to the FPGA port of the Flash memory through the DMA channel. The microprocessor, the embedded Flash memory, the DMA channel and the S-RAM embedded FPGA are integrated as a single chip.
摘要翻译： 动态可重构处理单元包括微处理器和用于代码，数据和比特流的非易失性存储的嵌入式闪存。 嵌入式闪存包括现场可编程门阵列（FPGA）端口。 可重构处理单元还包括直接存储器访问（DMA）通道和用于FPGA重新配置的S-RAM嵌入式FPGA。 S-RAM嵌入式FPGA具有通过DMA通道连接到闪存的FPGA端口的FPGA编程接口。 微处理器，嵌入式闪存，DMA通道和S-RAM嵌入式FPGA集成为单芯片。
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