公开(公告)号：US5899732A

公开(公告)日：1999-05-04

申请号：US837937

申请日：1997-04-11

申请人： Mark I. Gardner ,  Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore

发明人： Mark I. Gardner ,  Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore

IPC分类号： H01L21/225 ,  H01L21/265 ,  H01L21/322 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/10

CPC分类号： H01L29/66492 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/3221 ,  H01L21/8238 ,  H01L29/1083 ,  H01L29/6659

摘要： A region of damaged silicon is exploited as a gettering region for gettering impurities in a silicon substrate. The region of damaged silicon is formed between source and drain regions of a device by implanting silicon atoms into the silicon substrate after the formation of a gate electrode of the device. The damaged region is subsequently annealed and, during the annealing process, dopant atoms such as boron segregate to the region, locally increasing the dopant concentration in the region. The previously damaged region is in a location that determine the punchthrough characteristics of the device. The silicon implant for creating a gettering effect is performed after gate formation so that the region immediately beneath the junction is maintained at a lower dopant concentration to reduce junction capacitance. Silicon is implanted in the vicinity of a polysilicon gate to induce transient-enhanced diffusion (TED) of dopant atoms such as boron or phosphorus for control of punchthrough characteristics of a device. A punchthrough control implant is performed following formation of gate electrodes on a substrate using a self-aligned gettering implant.

摘要翻译： 受损硅的区域被用作吸杂硅衬底中的杂质的吸杂区域。 损坏的硅的区域在器件的栅极电极形成之后通过将硅原子注入到硅衬底中而在器件的源极和漏极区域之间形成。 受损区域随后退火，并且在退火过程期间，诸如硼的掺杂剂原子偏析到该区域，局部地增加该区域中的掺杂剂浓度。 先前损坏的区域位于确定设备穿透特性的位置。 用于产生吸杂效应的硅植入物在栅极形成之后进行，使得紧邻在结点处的区域保持在较低掺杂剂浓度以减小结电容。 将硅注入到多晶硅栅极附近以引发诸如硼或磷的掺杂剂原子的瞬态增强扩散（TED），以控制器件的穿透特性。 在使用自对准吸气植入物在衬底上形成栅电极之后执行穿通控制植入。

公开(公告)号：US5888675A

公开(公告)日：1999-03-30

申请号：US760031

申请日：1996-12-04

申请人： Bradley T. Moore ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Mark W. Michael ,  Derick J. Wristers

发明人： Bradley T. Moore ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Mark W. Michael ,  Derick J. Wristers

IPC分类号： G03F1/00 ,  G03F7/20 ,  H01L21/027 ,  G03F9/00 ,  G03C5/00

CPC分类号： G03F7/70433 ,  G03F1/70 ,  G03F7/70241

摘要： A reticle provides an image pattern and compensates for a lens error in a photolithographic system. The reticle is structurally modified using image displacement data indicative of the lens error. The reticle can be structurally modified by adjusting the configuration (or layout) of radiation-transmitting regions, for instance by adjusting a chrome pattern on the top surface of a quartz base. Alternatively, the reticle can be structurally modified by adjusting the curvature of the reticle, for instance by providing a chrome pattern on the top surface of a quartz base and grinding away portions of the bottom surface of the quartz base. The image displacement data may also vary as a function of lens heating so that the reticle compensates for lens heating associated with the reticle pattern.

摘要翻译： 掩模版提供图像图案并补偿光刻系统中的透镜误差。 使用指示透镜误差的图像位移数据对结构上的掩模版进行修改。 可以通过调节辐射透射区域的构造（或布局）来结构地修改掩模版，例如通过调节石英基底的顶表面上的铬图案。 或者，可以通过调整掩模版的曲率来结构地修改掩模版，例如通过在石英基底的顶表面上提供铬图案并研磨掉石英基底的底表面的部分。 图像位移数据也可以根据透镜加热而变化，使得掩模版补偿与标线图案相关联的透镜加热。

公开(公告)号：US06372588B2

公开(公告)日：2002-04-16

申请号：US08837523

申请日：1997-04-21

申请人： Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore

发明人： Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore

IPC分类号： H01L21336

CPC分类号： H01L29/66575 ,  H01L21/2256 ,  H01L21/32155 ,  H01L29/665

摘要： A method of making an IGFET using solid phase diffusion is disclosed. The method includes providing a device region in a semiconductor substrate, forming a gate insulator on the device region, forming a gate on the gate insulator, forming an insulating layer over the gate and the device region, forming a heavily doped diffusion source layer over the insulating layer, and driving a dopant from the diffusion source layer through the insulating layer into the gate and the device region by solid phase diffusion, thereby heavily doping the gate and forming a heavily doped source and drain in the device region. Preferably, the gate and diffusion source layer are polysilicon, the gate insulator and insulating layer are silicon dioxide, the dopant is boron or boron species, and the dopant provides essentially all P-type doping for the gate, source and drain, thereby providing shallow channel junctions and reducing or eliminating boron penetration from the gate into the substrate.

摘要翻译： 公开了使用固相扩散制造IGFET的方法。 该方法包括在半导体衬底中提供器件区域，在器件区域上形成栅极绝缘体，在栅极绝缘体上形成栅极，在栅极和器件区域上形成绝缘层，在其上形成重掺杂扩散源层 绝缘层，并且通过固相扩散将掺杂剂从扩散源层驱动通过绝缘层进入栅极和器件区域，从而大量掺杂栅极并在器件区域中形成重掺杂的源极和漏极。 优选地，栅极和扩散源层是多晶硅，栅绝缘体和绝缘层是二氧化硅，掺杂剂是硼或硼物质，并且掺杂剂为栅极，源极和漏极提供基本上所有的P型掺杂，从而提供浅 通道结并且减少或消除从孔进入衬底的硼渗透。

公开(公告)号：US06259142B1

公开(公告)日：2001-07-10

申请号：US09056837

申请日：1998-04-07

申请人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L2976

CPC分类号： H01L29/66484 ,  H01L29/7831

摘要： A semiconductor integrated circuit having a multiple split gate is forming using a first polysilicon layer and a second polysilicon layer to form alternating first and second gate electrodes within an active area. The alternating gate electrodes are electrically isolated from one another by means of a gate insulating layer that is formed adjacent the side-walls of each firs gate electrode. Source and drain regions are formed adjacent the ends of the multiple split gate to define a channel region.

摘要翻译： 具有多个分割栅极的半导体集成电路使用第一多晶硅层和第二多晶硅层形成，以在有源区内形成交替的第一和第二栅电极。 交替的栅电极通过与每个第一栅电极的侧壁相邻形成的栅极绝缘层彼此电隔离。 源极和漏极区域形成在多分裂栅极的端部附近以限定沟道区域。

公开(公告)号：US06201278B1

公开(公告)日：2001-03-13

申请号：US09028896

申请日：1998-02-24

申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L31062

CPC分类号： H01L29/7834 ,  H01L29/66621

摘要： An IGFET with a gate electrode and insulative spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, and insulative spacers between the gate electrode and the sidewalls. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, depositing a blanket layer of insulative spacer material over the substrate and applying an anisotropic etch to form the insulative spacers on the sidewalls, growing the gate insulator on a central portion of the bottom surface between the insulative spacers, depositing a gate electrode material on the gate insulator and the insulative spacers, polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate, and applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, thereby forming a source and drain with channel junctions substantially aligned with the gate electrode. Advantageously, the channel length is significantly smaller than the trench length.

摘要翻译： 公开了一种具有栅电极和沟槽中的绝缘间隔物的IGFET。 IGFET包括具有相对侧壁的沟槽和半导体衬底中的底表面，底表面上的栅极绝缘体，栅极绝缘体上的栅极电极以及栅电极和侧壁之间的绝缘间隔物。 形成IGFET的方法包括将掺杂层注入到衬底中，通过掺杂层完全蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分为源极和漏极区，将绝缘隔离材料的覆盖层沉积在 基板并施加各向异性蚀刻以在侧壁上形成绝缘间隔物，在绝缘隔离物之间的底表面的中心部分上生长栅极绝缘体，在栅极绝缘体上沉积栅电极材料和绝缘间隔物，抛光栅极 电极材料，使得栅电极基本上与衬底的顶表面对准，并施加高温退火以扩散底表面下面的源极和漏极区域，从而形成源极和漏极，其通道结基本上与 栅电极。 有利地，沟道长度明显小于沟槽长度。

公开(公告)号：US6100146A

公开(公告)日：2000-08-08

申请号：US739595

申请日：1996-10-30

申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/7834 ,  H01L29/66621

摘要： An IGFET with a gate electrode and insulative spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, and insulative spacers between the gate electrode and the sidewalls. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, depositing a blanket layer of insulative spacer material over the substrate and applying an anisotropic etch to form the insulative spacers on the sidewalls, growing the gate insulator on a central portion of the bottom surface between the insulative spacers, depositing a gate electrode material on the gate insulator and the insulative spacers, polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate, and applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, thereby forming a source and drain with channel junctions substantially aligned with the gate electrode. Advantageously, the channel length is significantly smaller than the trench length.

摘要翻译： 公开了一种具有栅电极和沟槽中的绝缘间隔物的IGFET。 IGFET包括具有相对侧壁的沟槽和半导体衬底中的底表面，底表面上的栅极绝缘体，栅极绝缘体上的栅极电极以及栅电极和侧壁之间的绝缘间隔物。 形成IGFET的方法包括将掺杂层注入到衬底中，通过掺杂层完全蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分为源极和漏极区，将绝缘隔离材料的覆盖层沉积在 基板并施加各向异性蚀刻以在侧壁上形成绝缘间隔物，在绝缘隔离物之间的底表面的中心部分上生长栅极绝缘体，在栅极绝缘体上沉积栅电极材料和绝缘间隔物，抛光栅极 电极材料，使得栅电极基本上与衬底的顶表面对准，并施加高温退火以扩散底表面下面的源极和漏极区域，从而形成源极和漏极，其通道结基本上与 栅电极。 有利地，沟道长度明显小于沟槽长度。

公开(公告)号：US06080629A

公开(公告)日：2000-06-27

申请号：US837579

申请日：1997-04-21

申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823842 ,  H01L21/28035

摘要： A method for implanting a dopant into a thin gate electrode layer includes forming a displacement layer on the gate electrode layer to form a combined displacement/gate electrode layer, and implanting the dopant into the combined layer. The implanted dopant profile may substantially reside entirely within the gate electrode layer, or may substantially reside partially within the gate electrode layer and partially within the displacement layer. If the displacement layer is ultimately removed, at least some portion of the implanted dopant remains within the gate electrode layer. The gate electrode layer may be implanted before or after patterning and etching the gate electrode layer to define gate electrodes. Moreover, two different selective implants may be used to define separate regions of differing dopant concentration, such as P-type polysilicon and N-type polysilicon regions. Each region may utilize separate displacement layer thicknesses, which allows dopants of different atomic mass to use similar implant energies. A higher implant energy may be used to dope a gate electrode layer which is much thinner than normal range statistics require, without implant penetration into underlying structures.

摘要翻译： 将掺杂剂注入到薄栅电极层中的方法包括在栅电极层上形成位移层以形成组合位移/栅极电极层，并将掺杂剂注入到组合层中。 注入的掺杂剂分布基本上完全位于栅极电极层内，或者基本上部分地位于栅极电极层内部分地位于位移层内。 如果位移层最终被去除，则注入的掺杂剂的至少一部分保留在栅电极层内。 栅极电极层可以在图案化之前或之后被注入，并蚀刻栅电极层以限定栅电极。 此外，可以使用两种不同的选择性植入来限定不同掺杂剂浓度的分开的区域，例如P型多晶硅和N型多晶硅区域。 每个区域可以利用单独的位移层厚度，这允许不同原子质量的掺杂剂使用类似的注入能量。 可以使用较高的注入能量来掺杂比正常范围统计要求更薄的栅极电极层，而不会使植入物渗入下面的结构。

公开(公告)号：US6048785A

公开(公告)日：2000-04-11

申请号：US876628

申请日：1997-06-16

申请人： H. Jim Fulford, Jr. ,  Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： H. Jim Fulford, Jr. ,  Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76895 ,  Y10S438/946 ,  Y10S438/949

摘要： Each region of multiple regions on a semiconductor substrate is imaged in an exposure field defined by a reticle. The regions are separated and electrically isolated within the semiconductor substrate by an isolation such as a field oxide or trench isolation. The regions are interconnected by imaging using a stitching reticle having an exposure field overlapping a plurality of the regions. The combination of reticle-imaged fields effectively increases the size of a field formed using a step and repeat technique while achieving high imaging resolution within the combined regions. Similarly, a plurality of integrated chip sets, including microprocessor, memory, and support chips, are constructed on a single semiconductor wafer using separate reticle imaging of each of the plurality of integrated chip sets. The different circuits are interconnected using a stitch mask and etch operation that combines the regions.

摘要翻译： 在半导体衬底上的多个区域的每个区域以由掩模版定义的曝光区域成像。 这些区域通过诸如场氧化物或沟槽隔离的隔离在半导体衬底内分离和电隔离。 这些区域通过使用具有与多个区域重叠的曝光场的拼接掩模版进行成像来互连。 掩模版成像场的组合有效地增加了使用步骤和重复技术形成的场的大小，同时在组合区域内实现高成像分辨率。 类似地，使用多个集成芯片组中的每一个的单独掩模版成像，在单个半导体晶片上构造包括微处理器，存储器和支持芯片的多个集成芯片组。 使用组合这些区域的针迹掩模和蚀刻操作来使不同的电路互连。

公开(公告)号：US5937299A

公开(公告)日：1999-08-10

申请号：US837522

申请日：1997-04-21

申请人： Mark W. Michael ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark W. Michael ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L29/6659 ,  H01L21/28114 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/66628 ,  H01L29/665

摘要： An IGFET with source and drain contacts in close proximity to a gate with sloped sidewalls is disclosed. A method of making the IGFET includes forming a gate over a semiconductor substrate, wherein the gate includes a top surface, a bottom surface and opposing sidewalls, and the top surface has a substantially greater length than the bottom surface, forming a source and a drain that extend into the substrate, depositing a contact material over the gate, source and drain, and forming a gate contact on the gate, a source contact on the source, and a drain contact on the drain. The gate is separated from the source and drain contacts due to a retrograde slope of the gate sidewalls, and the gate contact is separated from the source and drain contacts due to a lack of step coverage in the contact material. Preferably, the contact material is a refractory metal, and the contacts are formed by converting the refractory metal into a silicide. In this manner, a highly miniaturized IGFET can be provided with densely-packed gate, source and drain contacts without the need for sidewall spacers adjacent to the gate.

摘要翻译： 公开了具有源极和漏极触点的IGFET，其紧邻具有倾斜侧壁的栅极。 制造IGFET的方法包括在半导体衬底上形成栅极，其中栅极包括顶表面，底表面和相对的侧壁，并且顶表面具有比底表面大得多的长度，形成源极和漏极 延伸到衬底中，在栅极，源极和漏极上沉积接触材料，以及在栅极上形成栅极接触，源极上的源极接触和漏极上的漏极接触。 由于栅极侧壁的逆向斜坡，栅极与源极和漏极接触分离，并且由于接触材料中缺少台阶覆盖，栅极接触与源极和漏极接触分离。 优选地，接触材料是难熔金属，并且通过将难熔金属转化为硅化物形成触点。 以这种方式，高度小型化的IGFET可以设置有密集封装的栅极，源极和漏极接触，而不需要邻近栅极的侧壁间隔。

公开(公告)号：US5918126A

公开(公告)日：1999-06-29

申请号：US805796

申请日：1997-02-25

申请人： H. Jim Fulford, Jr. ,  Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： H. Jim Fulford, Jr. ,  Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L21/8234

CPC分类号： H01L21/32139 ,  H01L21/28123 ,  H01L21/823456

摘要： It has been discovered that different pattern densities that occur in conventional lithography produce a different final etch polysilicon gate width in high density (dense) regions of polysilicon gates as compared to low density (isolated) polysilicon gate regions. The final etch polysilicon gate width for a dense region is smaller by a predictable distance relative to the final etch polysilicon gate width for an isolated region. For example, a typical dense region has a final etch polysilicon gate width that is approximately 0.05 .mu.m smaller relative to the final etch polysilicon gate width of isolated regions having a channel length of 0.35 .mu.m. A biasing technique is employed for a polysilicon masking reticle in which the reticle is biased differently in regions of isolated polysilicon gates in comparison to regions of dense polysilicon gates. More specifically, in one embodiment the polysilicon masking reticle is increased in size in regions of high density polysilicon gates in comparison to regions of isolated polysilicon gates. In another embodiment, the reticle in regions of isolated polysilicon gates is sized normally but increased in size in regions of high density polysilicon gates. Following photomasking and etching, substantially identical polysilicon lengths are achieved in the isolated and dense gate regions.

摘要翻译： 已经发现，与低密度（隔离）多晶硅栅极区域相比，在常规光刻中发生的不同图案密度在多晶硅栅极的高密度（密集）区域中产生不同的最终蚀刻多晶硅栅极宽度。 用于密集区域的最终蚀刻多晶硅栅极宽度相对于隔离区域的最终蚀刻多晶硅栅极宽度可预测的距离较小。 例如，典型的密集区域具有最终蚀刻多晶硅栅极宽度，相对于沟道长度为0.35μm的隔离区域的最终蚀刻多晶硅栅极宽度大约为0.05μm。 对于多晶硅掩模掩模版采用偏置技术，其中与致密多晶硅栅极的区域相比，掩模版在隔离多晶硅栅极的区域中被不同地偏置。 更具体地，在一个实施例中，与隔离多晶硅栅极的区域相比，多晶硅掩模掩模版的尺寸在高密度多晶硅栅极的区域中增加。 在另一个实施例中，隔离多晶硅栅极的区域中的掩模版尺寸正常，但在高密度多晶硅栅极的区域中的尺寸增大。 在光掩模和蚀刻之后，在隔离和密集的栅极区域中实现了基本相同的多晶硅长度。