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    Semiconductor Memory Chip
    21.
    发明申请
    Semiconductor Memory Chip 失效
    半导体存储芯片

    公开(公告)号：US20070217268A1

    公开(公告)日：2007-09-20

    申请号：US11751984

    申请日：2007-05-22

    申请人： Paul Wallner ,  Martin Streibl ,  Manfred Menke ,  Yukio Fukuzo ,  Christian Sichert ,  Peter Gregorius

    发明人： Paul Wallner ,  Martin Streibl ,  Manfred Menke ,  Yukio Fukuzo ,  Christian Sichert ,  Peter Gregorius

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1006 ,  G11C11/4096

    摘要： A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

    摘要翻译： 半导体存储器芯片包括：接收接口部分，用于以串行信号帧的形式接收外部数据，命令和地址信号; 中间数据缓冲器，用于中间存储写入数据，以及可选地写入要写入存储单元阵列的数据屏蔽位; 具有存储体组织的存储单元阵列的存储器核心; 解码器部分，用于对从接收接口部分接收的信号帧导出的地址进行解码，用于根据在一个或多个接收信号中的写入/读取命令向/从存储器单元阵列的一个或多个存储器组写入/读取数据 框架 以及帧解码器，被设置为在接收接口部分和存储器核心之间的接口，用于对包括在一个或多个帧中的一个或多个命令进行解码，并将数据地址，命令和读/写访问指示信号输出到存储器核心和 中间数据缓冲区。

    SEMICONDUCTOR MEMORY CHIP
    23.
    发明申请
    SEMICONDUCTOR MEMORY CHIP 有权
    半导体内存芯片

    公开(公告)号：US20070076508A1

    公开(公告)日：2007-04-05

    申请号：US11242150

    申请日：2005-10-04

    申请人： Paul Wallner ,  Martin Streibl ,  Manfred Menke ,  Yukio Fukuzo ,  Christian Sichert ,  Peter Gregorius

    发明人： Paul Wallner ,  Martin Streibl ,  Manfred Menke ,  Yukio Fukuzo ,  Christian Sichert ,  Peter Gregorius

    IPC分类号： G11C8/00

    CPC分类号： G11C7/1006 ,  G11C11/4096

    摘要： A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

    摘要翻译： 半导体存储器芯片包括：接收接口部分，用于以串行信号帧的形式接收外部数据，命令和地址信号; 中间数据缓冲器，用于中间存储写入数据，以及可选地写入要写入存储单元阵列的数据屏蔽位; 具有存储体组织的存储单元阵列的存储器核心; 解码器部分，用于对从接收接口部分接收的信号帧导出的地址进行解码，用于根据在一个或多个接收信号中的写入/读取命令向/从存储器单元阵列的一个或多个存储器组写入/读取数据 框架 以及帧解码器，被设置为在接收接口部分和存储器核心之间的接口，用于解码包括在一个或多个帧中的一个或多个命令，并将数据地址，命令和读/写访问指示信号输出到存储器核心 中间数据缓冲区。

    High-speed interface circuit for semiconductor memory chips and memory system including semiconductor memory chips
    24.
    发明授权
    High-speed interface circuit for semiconductor memory chips and memory system including semiconductor memory chips 有权
    用于半导体存储器芯片的高速接口电路和包括半导体存储器芯片的存储器系统

    公开(公告)号：US07184360B2

    公开(公告)日：2007-02-27

    申请号：US11152769

    申请日：2005-06-15

    申请人： Peter Gregorius ,  Martin Streibl ,  Paul Wallner ,  Thomas Rickes

    发明人： Peter Gregorius ,  Martin Streibl ,  Paul Wallner ,  Thomas Rickes

    IPC分类号： G11C8/00

    CPC分类号： G06F13/4243 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/107

    摘要： A high-speed interface circuit is implemented in a semiconductor memory chip including a memory core, a first interface circuit section, and a second interface circuit section. The first interface circuit section is connectable to a write data-/command and address signal bus, includes a write data-/command and address re-driver/transmitter path (which may be transparent) and does not include any clock signal synchronizing circuitry, and a main write signal path including a serial-to-parallel converting and synchronizing device to synchronize with a reference clock signal received write data-/command and address signals and delivering the parallel converted write signals to the memory core. The second interface circuit section is connectable to a read data bus and includes a transparent read data re-driver/transmitter path for transmitting and re-driving received serial read data to a succeeding semiconductor memory chip and a main read signal path for inserting the parallel-to-serial converted read data from the memory core into the received serial read data stream, synchronizing the parallel-to-serial converted read data with the reference clock signal and providing the serialized read data stream to a serial read data input terminal of a corresponding second interface circuit section of a succeeding same memory chip or to a memory controller.

    摘要翻译： 在包括存储器核心，第一接口电路部分和第二接口电路部分的半导体存储器芯片中实现高速接口电路。 第一接口电路部分可连接到写数据/命令和地址信号总线，包括写数据/命令和地址重新驱动器/发射机路径（其可以是透明的）并且不包括任何时钟信号同步电路， 以及包括串行到并行转换和同步装置的主写信号路径，以与接收到的写数据/命令和地址信号的参考时钟信号同步并将并行转换的写入信号传送到存储器核。 第二接口电路部分可连接到读数据总线，并且包括用于将接收的串行读取数据发送和重新驱动到后续半导体存储器芯片的透明读取数据重新驱动器/发送器路径和用于插入并行的主读取信号路径 将串行转换的读取数据从存储器核心转换成接收到的串行读取数据流，将并行到串行转换的读取数据与参考时钟信号同步，并将串行读取数据流提供给串行读取数据输入端 相应的相同存储器芯片的相应的第二接口电路部分或存储器控制器。

    Memory device and memory system comprising a memory device and a memory control device
    27.
    发明授权
    Memory device and memory system comprising a memory device and a memory control device 有权
    存储器件和存储器系统，包括存储器件和存储器控制器件

    公开(公告)号：US08031539B2

    公开(公告)日：2011-10-04

    申请号：US12248759

    申请日：2008-10-09

    申请人： Peter Gregorius

    发明人： Peter Gregorius

    IPC分类号： G11C7/00

    CPC分类号： G11C5/00 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

    摘要： In an embodiment, a memory device comprises a clock generating unit being configured to generate a read clock signal, the clock generating unit being connected to a first clock signal contact configured to send the read clock signal, and the clock generating unit being connected to data signal contacts being configured to send data signals, the memory device being configured to send the data signals in a phase and frequency accurate (source synchronous) manner with regard to the read clock signal.

    摘要翻译： 在一个实施例中，存储器件包括时钟产生单元，其被配置为产生读取时钟信号，所述时钟产生单元连接到被配置为发送读取时钟信号的第一时钟信号触点，并且所述时钟产生单元连接到数据 信号触点被配置为发送数据信号，所述存储器件被配置为相对于读时钟信号以相位和频率精确（源同步）方式发送数据信号。

    Training connections in a memory arrangement
    28.
    发明授权
    Training connections in a memory arrangement 有权
    训练连接在内存安排

    公开(公告)号：US07908232B2

    公开(公告)日：2011-03-15

    申请号：US11844791

    申请日：2007-08-24

    申请人： Peter Gregorius

    发明人： Peter Gregorius

    IPC分类号： G06F15/18

    CPC分类号： G06F13/1684

    摘要： A method of training connections in a memory arrangement includes training a connection between a memory section and a receiver portion of a controller for controlling the memory arrangement before or simultaneously with a training of essentially all other connections between elements of the memory arrangement that are to be trained.

    摘要翻译： 训练存储器装置中的连接的方法包括训练存储器部分和控制器的接收器部分之间的连接，用于在存储器装置的元件之间的基本上所有其他连接的训练之前或同时进行控制， 训练有素