公开(公告)号：US08288293B2

公开(公告)日：2012-10-16

申请号：US12763963

申请日：2010-04-20

申请人： Tuan Pham ,  Sanghyun Lee ,  Masato Horiike ,  Klaus Schuegraf ,  Masaaki Higashitani ,  Keiichi Isono

发明人： Tuan Pham ,  Sanghyun Lee ,  Masato Horiike ,  Klaus Schuegraf ,  Masaaki Higashitani ,  Keiichi Isono

IPC分类号： H01L21/469

CPC分类号： H01L27/11548 ,  H01L21/2815 ,  H01L27/11529 ,  H01L29/66825

摘要： Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.

摘要翻译： 半导体器件设置有用于在制造工艺期间保护侧壁特征的封装膜，例如蚀刻以形成隔离区域。 在非易失性闪速存储器中，例如，沟槽隔离工艺被分成段以沿着电荷存储材料的侧壁并入封装膜。 在层堆叠上形成图案，随后蚀刻电荷存储材料，以形成沿着衬底的列方向延伸的条带，其间具有隧道介电材料层。 在蚀刻基板之前，沿着电荷存储材料条的侧壁形成封装膜。 封装膜可以在随后的清洁，氧化和蚀刻工艺期间保护电荷存储材料的侧壁。 在另一个实例中，同时形成封装膜，同时蚀刻以形成电荷存储材料条和隔离槽。

公开(公告)号：US20120228691A1

公开(公告)日：2012-09-13

申请号：US13072130

申请日：2011-03-25

申请人： Mohan Dunga ,  Sanghyun Lee ,  Masaaki Higashitani ,  Tuan Pham

发明人： Mohan Dunga ,  Sanghyun Lee ,  Masaaki Higashitani ,  Tuan Pham

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L21/28

CPC分类号： H01L29/66825 ,  G11C11/5642 ,  G11C16/0408 ,  G11C16/3418 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/40114 ,  H01L29/7881

摘要： Non-volatile storage elements having a PN floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have an N+ region near the control gate. In some embodiments, a P− region near the tunnel oxide helps provide good data retention. In some embodiments, an N+ region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.

摘要翻译： 本文公开了具有PN浮动栅极的非易失性存储元件。 浮置栅极可以在隧道氧化物附近具有P-区域，并且可以在控制栅极附近具有N +区域。 在一些实施例中，隧道氧化物附近的P-区域有助于提供良好的数据保留。 在一些实施例中，控制栅极附近的N +区域有助于实现控制栅极和浮置栅极之间良好的耦合比。 因此，非易失性存储元件的编程是有效的。 也可以有效地擦除非易失性存储元件。 在一些实施例中，在隧道氧化物附近具有P-区（与强掺杂p型半导体相反）可提高相对于P +的擦除效率。

公开(公告)号：US20100270608A1

公开(公告)日：2010-10-28

申请号：US12763963

申请日：2010-04-20

申请人： Tuan Pham ,  Sanghyun Lee ,  Masato Horiike ,  Klaus Schuegraf ,  Masaaki Higashitani ,  Keiichi Isono

发明人： Tuan Pham ,  Sanghyun Lee ,  Masato Horiike ,  Klaus Schuegraf ,  Masaaki Higashitani ,  Keiichi Isono

IPC分类号： H01L29/792 ,  H01L21/28 ,  H01L21/76

CPC分类号： H01L27/11548 ,  H01L21/2815 ,  H01L27/11529 ,  H01L29/66825

摘要： Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.

摘要翻译： 半导体器件设置有用于在制造工艺期间保护侧壁特征的封装膜，例如蚀刻以形成隔离区域。 在非易失性闪速存储器中，例如，沟槽隔离工艺被分成段以沿着电荷存储材料的侧壁并入封装膜。 在层堆叠上形成图案，随后蚀刻电荷存储材料，以形成沿着衬底的列方向延伸的条带，其间具有隧道介电材料层。 在蚀刻基板之前，沿着电荷存储材料条的侧壁形成封装膜。 封装膜可以在随后的清洁，氧化和蚀刻工艺期间保护电荷存储材料的侧壁。 在另一个实例中，同时形成封装膜，同时蚀刻以形成电荷存储材料条和隔离槽。

公开(公告)号：US20100047979A1

公开(公告)日：2010-02-25

申请号：US12567257

申请日：2009-09-25

申请人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

发明人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/3205

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures.

摘要翻译： 非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。 相邻的串由浅沟槽隔离结构隔离。

公开(公告)号：US07592223B2

公开(公告)日：2009-09-22

申请号：US12061642

申请日：2008-04-02

申请人： Tuan Pham ,  Takashi Orimoto ,  Masaaki Higashitani ,  James Kai ,  George Matamis

发明人： Tuan Pham ,  Takashi Orimoto ,  Masaaki Higashitani ,  James Kai ,  George Matamis

IPC分类号： H01L21/8247

CPC分类号： H01L27/11543 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11541

摘要： Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming the same using integrated select and peripheral circuitry formation are provided. Strips of charge storage material elongated in a column direction across the surface of a substrate with strips of tunnel dielectric material therebetween are formed. The strips of charge storage material can include multiple layers of charge storage material to form composite charge storage structures in one embodiment. After forming isolation trenches in the substrate between active areas below the strips of charge storage material, spacer-assisted patterning is used to form a pattern at the memory array region. Strips of photoresist are patterned over a portion of the pattern at the memory array. Photoresist is also applied at the peripheral circuitry region. At least a portion of the layer stack is etched using the photoresist as a mask before removing the photoresist and etching the strips of charge storage material to form the charge storage structures.

摘要翻译： 提供了具有双控制栅极存储器单元的非易失性半导体存储器件及其使用集成选择和外围电路形成的方法。 形成沿着柱方向延伸穿过衬底表面的电荷存储材料带，其间具有隧道介电材料带。 在一个实施例中，电荷存储材料条可以包括多层电荷存储材料以形成复合电荷存储结构。 在电荷存储材料条带之下的有源区域中的衬底中形成隔离沟槽之后，使用间隔物辅助图案化以在存储器阵列区域形成图案。 在存储器阵列上的图案的一部分上图案化的光致抗蚀剂条纹。 光刻胶也被应用在外围电路区域。 在去除光致抗蚀剂并蚀刻电荷存储材料条之前，使用光致抗蚀剂作为掩模来蚀刻层叠体的至少一部分，以形成电荷存储结构。

公开(公告)号：US07482223B2

公开(公告)日：2009-01-27

申请号：US11020402

申请日：2004-12-22

申请人： Masaaki Higashitani ,  Tuan Pham

发明人： Masaaki Higashitani ,  Tuan Pham

IPC分类号： H01L21/336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546

摘要： A process provides a gate dielectric layer of a first thickness for a memory array and for certain peripheral circuits on the same substrate as the memory array. High-voltage peripheral circuits are provided with a gate dielectric layer of a second thickness. Low-voltage peripheral circuits are provided with a gate dielectric layer of a third thickness. The process provides protection from subsequent process steps for a gate dielectric layer. Shallow trench isolation allows the memory array cells to be extremely small, thus providing high storage density.

摘要翻译： 一种工艺为存储器阵列和与存储器阵列相同的衬底上的某些外围电路提供第一厚度的栅介质层。 高电压外围电路设置有第二厚度的栅极电介质层。 低电压外围电路设置有第三厚度的栅极电介质层。 该方法提供了对于栅极电介质层的后续工艺步骤的保护。 浅沟槽隔离允许存储器阵列单元非常小，从而提供高的存储密度。

公开(公告)号：US20080268596A1

公开(公告)日：2008-10-30

申请号：US12061642

申请日：2008-04-02

申请人： Tuan Pham ,  Takashi Orimoto ,  Masaaki Higashitani ,  James Kai ,  George Matamis

发明人： Tuan Pham ,  Takashi Orimoto ,  Masaaki Higashitani ,  James Kai ,  George Matamis

IPC分类号： H01L21/336

CPC分类号： H01L27/11543 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11541

摘要： Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming the same using integrated select and peripheral circuitry formation are provided. Strips of charge storage material elongated in a column direction across the surface of a substrate with strips of tunnel dielectric material therebetween are formed. The strips of charge storage material can include multiple layers of charge storage material to form composite charge storage structures in one embodiment. After forming isolation trenches in the substrate between active areas below the strips of charge storage material, spacer-assisted patterning is used to form a pattern at the memory array region. Strips of photoresist are patterned over a portion of the pattern at the memory array. Photoresist is also applied at the peripheral circuitry region. At least a portion of the layer stack is etched using the photoresist as a mask before removing the photoresist and etching the strips of charge storage material to form the charge storage structures.

摘要翻译： 提供了具有双控制栅极存储器单元的非易失性半导体存储器件及其使用集成选择和外围电路形成的方法。 形成沿着柱方向延伸穿过衬底表面的电荷存储材料带，其间具有隧道介电材料带。 在一个实施例中，电荷存储材料条可以包括多层电荷存储材料以形成复合电荷存储结构。 在电荷存储材料条带之下的有源区域中的衬底中形成隔离沟槽之后，使用间隔物辅助图案化以在存储器阵列区域形成图案。 在存储器阵列上的图案的一部分上图案化的光致抗蚀剂条纹。 光刻胶也被应用在外围电路区域。 在去除光致抗蚀剂并蚀刻电荷存储材料条之前，使用光致抗蚀剂作为掩模来蚀刻层叠体的至少一部分，以形成电荷存储结构。

公开(公告)号：US20070147119A1

公开(公告)日：2007-06-28

申请号：US11319908

申请日：2005-12-27

申请人： Tuan Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Hemink

发明人： Tuan Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Hemink

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11534

摘要： A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.

摘要翻译： NAND闪存器件采用独特的增压板设计。 升压板在读取和编程操作期间被偏置，并且在许多情况下与浮动栅极的耦合降低了编程和读取存储在栅极中的电荷所需的电压电平。 升压板还屏蔽浮动栅极之间的不必要的耦合。 自升压，局部自升压，以及独特升压板使用的擦除区域自升压模式，进一步提高了读/写可靠性和精度。 因此，根据本发明可以实现更紧凑和可靠的存储器件。

公开(公告)号：US20060134845A1

公开(公告)日：2006-06-22

申请号：US11021693

申请日：2004-12-22

申请人： Tuan Pham ,  Masaaki Higashitani

发明人： Tuan Pham ,  Masaaki Higashitani

IPC分类号： H01L21/8238

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： A method of making a memory array and peripheral circuits together on a single substrate forms a dielectric layer, floating gate layer, inter-layer dielectric and mask layer across all regions of the substrate. Subsequently these layers are removed from the peripheral regions and dielectrics of different thicknesses are formed in the peripheral regions according to the voltages of the circuits in these regions. A conductive layer is formed over the memory array and the peripheral circuits to form control gates in the memory array and form gate electrodes in the peripheral regions.

摘要翻译： 将存储器阵列和外围电路一起制成单个衬底的方法在衬底的所有区域上形成介电层，浮栅，层间电介质和掩模层。 随后，这些层从外围区域移除，并且根据这些区域中的电路的电压在周边区域中形成不同厚度的电介质。 在存储器阵列和外围电路上形成导电层，以在存储器阵列中形成控制栅极并在外围区域中形成栅电极。

公开(公告)号：US20050199939A1

公开(公告)日：2005-09-15

申请号：US10799060

申请日：2004-03-12

申请人： Jeffrey Lutze ,  Tuan Pham ,  Masaaki Higashitani

发明人： Jeffrey Lutze ,  Tuan Pham ,  Masaaki Higashitani

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L29/788

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521

摘要： A non-volatile memory array has word lines coupled to floating gates, the floating gates having an upper portion that is adapted to provide increased surface area, and thereby, to provide increased coupling to the word lines. Shielding between floating gates is also provided. A first process forms floating gates by etching an upper portion of a polysilicon structure with masking elements in place to shape the floating gate. A second process etches recesses and protrusions in a polysilicon structure prior to etching the structure to form individual floating gates.

摘要翻译： 非易失性存储器阵列具有耦合到浮动栅极的字线，浮动栅极具有适于提供增加的表面积的上部部分，从而提供增加的与字线的耦合。 还提供了浮动门之间的屏蔽。 第一工艺通过用掩蔽元件蚀刻多晶硅结构的上部来形成浮栅来形成浮栅，以形成浮栅。 在蚀刻结构之前，第二工艺蚀刻多晶硅结构中的凹陷和突起以形成单独的浮动栅极。