公开(公告)号：US20120243337A1

公开(公告)日：2012-09-27

申请号：US13153964

申请日：2011-06-06

申请人： Sanghyun Lee ,  Mohan Dunga ,  Masaaki Higashitani ,  Tuan Pham ,  Franz Kreupl

发明人： Sanghyun Lee ,  Mohan Dunga ,  Masaaki Higashitani ,  Tuan Pham ,  Franz Kreupl

IPC分类号： G11C16/10 ,  G11C16/04 ,  H01L21/336 ,  H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/42324

摘要： Non-volatile storage elements having a P−/metal floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have a metal region near the control gate. A P− region near the tunnel oxide helps provide good data retention. A metal region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also, erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.

摘要翻译： 本文公开了具有P- /金属浮动栅极的非易失性存储元件。 浮栅可以在隧道氧化物附近具有P-区域，并且可以在控制栅极附近具有金属区域。 隧道氧化物附近的P-区域有助于提供良好的数据保留。 控制栅极附近的金属区域有助于实现控制栅极和浮动栅极之间良好的耦合比。 因此，非易失性存储元件的编程是有效的。 此外，擦除非易失性存储元件可能是有效的。 在一些实施例中，在隧道氧化物附近具有P-区（与强掺杂p型半导体相反）可提高相对于P +的擦除效率。

公开(公告)号：US08503229B2

公开(公告)日：2013-08-06

申请号：US13153964

申请日：2011-06-06

申请人： Sanghyun Lee ,  Mohan Dunga ,  Masaaki Higashitani ,  Tuan Pham ,  Franz Kreupl

发明人： Sanghyun Lee ,  Mohan Dunga ,  Masaaki Higashitani ,  Tuan Pham ,  Franz Kreupl

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L29/94 ,  H01L21/00 ,  H01L21/8238

CPC分类号： H01L21/28273 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/42324

摘要： Non-volatile storage elements having a P−/metal floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have a metal region near the control gate. A P− region near the tunnel oxide helps provide good data retention. A metal region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also, erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.

摘要翻译： 本文公开了具有P- /金属浮动栅极的非易失性存储元件。 浮栅可以在隧道氧化物附近具有P-区域，并且可以在控制栅极附近具有金属区域。 隧道氧化物附近的P-区域有助于提供良好的数据保留。 控制栅极附近的金属区域有助于实现控制栅极和浮动栅极之间良好的耦合比。 因此，非易失性存储元件的编程是有效的。 此外，擦除非易失性存储元件可能是有效的。 在一些实施例中，在隧道氧化物附近具有P-区（与强掺杂p型半导体相反）可提高相对于P +的擦除效率。

公开(公告)号：US20120228691A1

公开(公告)日：2012-09-13

申请号：US13072130

申请日：2011-03-25

申请人： Mohan Dunga ,  Sanghyun Lee ,  Masaaki Higashitani ,  Tuan Pham

发明人： Mohan Dunga ,  Sanghyun Lee ,  Masaaki Higashitani ,  Tuan Pham

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L21/28

CPC分类号： H01L29/66825 ,  G11C11/5642 ,  G11C16/0408 ,  G11C16/3418 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/40114 ,  H01L29/7881

摘要： Non-volatile storage elements having a PN floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have an N+ region near the control gate. In some embodiments, a P− region near the tunnel oxide helps provide good data retention. In some embodiments, an N+ region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.

摘要翻译： 本文公开了具有PN浮动栅极的非易失性存储元件。 浮置栅极可以在隧道氧化物附近具有P-区域，并且可以在控制栅极附近具有N +区域。 在一些实施例中，隧道氧化物附近的P-区域有助于提供良好的数据保留。 在一些实施例中，控制栅极附近的N +区域有助于实现控制栅极和浮置栅极之间良好的耦合比。 因此，非易失性存储元件的编程是有效的。 也可以有效地擦除非易失性存储元件。 在一些实施例中，在隧道氧化物附近具有P-区（与强掺杂p型半导体相反）可提高相对于P +的擦除效率。

公开(公告)号：US08853763B2

公开(公告)日：2014-10-07

申请号：US13607375

申请日：2012-09-07

申请人： Tuan Pham ,  Sanghyun Lee ,  Masato Horiike ,  Klaus Schuegraf ,  Masaaki Higashitani ,  Keiichi Isono

发明人： Tuan Pham ,  Sanghyun Lee ,  Masato Horiike ,  Klaus Schuegraf ,  Masaaki Higashitani ,  Keiichi Isono

IPC分类号： H01L29/76 ,  H01L27/115 ,  H01L29/66 ,  H01L21/28

CPC分类号： H01L27/11548 ,  H01L21/2815 ,  H01L27/11529 ,  H01L29/66825

摘要： Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.

摘要翻译： 半导体器件设置有用于在制造工艺期间保护侧壁特征的封装膜，例如蚀刻以形成隔离区域。 在非易失性闪速存储器中，例如，沟槽隔离工艺被分成段以沿着电荷存储材料的侧壁并入封装膜。 在层堆叠上形成图案，随后蚀刻电荷存储材料，以形成沿着衬底的列方向延伸的条带，其间具有隧道介电材料层。 在蚀刻基板之前，沿着电荷存储材料条的侧壁形成封装膜。 封装膜可以在随后的清洁，氧化和蚀刻工艺期间保护电荷存储材料的侧壁。 在另一个实例中，同时形成封装膜，同时蚀刻以形成电荷存储材料条和隔离槽。

公开(公告)号：US20120326220A1

公开(公告)日：2012-12-27

申请号：US13607375

申请日：2012-09-07

申请人： Tuan Pham ,  Sanghyun Lee ,  Masato Horiike ,  Klaus Schuegraf ,  Masaaki Higashitani ,  Keiichi Isono

发明人： Tuan Pham ,  Sanghyun Lee ,  Masato Horiike ,  Klaus Schuegraf ,  Masaaki Higashitani ,  Keiichi Isono

IPC分类号： H01L29/78

CPC分类号： H01L27/11548 ,  H01L21/2815 ,  H01L27/11529 ,  H01L29/66825

摘要： Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.

摘要翻译： 半导体器件设置有用于在制造工艺期间保护侧壁特征的封装膜，例如蚀刻以形成隔离区域。 在非易失性闪速存储器中，例如，沟槽隔离工艺被分成段以沿着电荷存储材料的侧壁并入封装膜。 在层堆叠上形成图案，随后蚀刻电荷存储材料，以形成沿着衬底的列方向延伸的条带，其间具有隧道介电材料层。 在蚀刻基板之前，沿着电荷存储材料条的侧壁形成封装膜。 封装膜可以在随后的清洁，氧化和蚀刻工艺期间保护电荷存储材料的侧壁。 在另一个实例中，同时形成封装膜，同时蚀刻以形成电荷存储材料条和隔离槽。

公开(公告)号：US08288293B2

公开(公告)日：2012-10-16

申请号：US12763963

申请日：2010-04-20

申请人： Tuan Pham ,  Sanghyun Lee ,  Masato Horiike ,  Klaus Schuegraf ,  Masaaki Higashitani ,  Keiichi Isono

发明人： Tuan Pham ,  Sanghyun Lee ,  Masato Horiike ,  Klaus Schuegraf ,  Masaaki Higashitani ,  Keiichi Isono

IPC分类号： H01L21/469

CPC分类号： H01L27/11548 ,  H01L21/2815 ,  H01L27/11529 ,  H01L29/66825

摘要： Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.

摘要翻译： 半导体器件设置有用于在制造工艺期间保护侧壁特征的封装膜，例如蚀刻以形成隔离区域。 在非易失性闪速存储器中，例如，沟槽隔离工艺被分成段以沿着电荷存储材料的侧壁并入封装膜。 在层堆叠上形成图案，随后蚀刻电荷存储材料，以形成沿着衬底的列方向延伸的条带，其间具有隧道介电材料层。 在蚀刻基板之前，沿着电荷存储材料条的侧壁形成封装膜。 封装膜可以在随后的清洁，氧化和蚀刻工艺期间保护电荷存储材料的侧壁。 在另一个实例中，同时形成封装膜，同时蚀刻以形成电荷存储材料条和隔离槽。

公开(公告)号：US20100270608A1

公开(公告)日：2010-10-28

申请号：US12763963

申请日：2010-04-20

申请人： Tuan Pham ,  Sanghyun Lee ,  Masato Horiike ,  Klaus Schuegraf ,  Masaaki Higashitani ,  Keiichi Isono

发明人： Tuan Pham ,  Sanghyun Lee ,  Masato Horiike ,  Klaus Schuegraf ,  Masaaki Higashitani ,  Keiichi Isono

IPC分类号： H01L29/792 ,  H01L21/28 ,  H01L21/76

CPC分类号： H01L27/11548 ,  H01L21/2815 ,  H01L27/11529 ,  H01L29/66825

摘要： Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.

摘要翻译： 半导体器件设置有用于在制造工艺期间保护侧壁特征的封装膜，例如蚀刻以形成隔离区域。 在非易失性闪速存储器中，例如，沟槽隔离工艺被分成段以沿着电荷存储材料的侧壁并入封装膜。 在层堆叠上形成图案，随后蚀刻电荷存储材料，以形成沿着衬底的列方向延伸的条带，其间具有隧道介电材料层。 在蚀刻基板之前，沿着电荷存储材料条的侧壁形成封装膜。 封装膜可以在随后的清洁，氧化和蚀刻工艺期间保护电荷存储材料的侧壁。 在另一个实例中，同时形成封装膜，同时蚀刻以形成电荷存储材料条和隔离槽。

公开(公告)号：US20130314995A1

公开(公告)日：2013-11-28

申请号：US13479649

申请日：2012-05-24

申请人： Deepanshu Dutta ,  Mohan Dunga ,  Masaaki Higashitani

发明人： Deepanshu Dutta ,  Mohan Dunga ,  Masaaki Higashitani

IPC分类号： G11C16/14 ,  G11C16/04

CPC分类号： G11C16/14 ,  G11C7/1006 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16

摘要： A technique for erasing non-volatile memory such as a NAND string which includes non-user data or dummy storage elements. The voltages of the non-user data storage elements are capacitively coupled higher by controlled increases in an erase voltage which is applied to a substrate. The voltages are floated by rendering a pass gate transistor in a non-conductive state, where the pass gate transistor is between a voltage driver and a non-user data storage element. Voltages of select gate transistors can also be capacitively coupled higher. The substrate voltage can be increased in steps and/or as a continuous ramp. In one approach, outer dummy storage elements are floated while inner dummy storage elements are driven. In another approach, both outer and inner dummy storage elements are floated. Write-erase endurance of the storage elements is increased due to reduced charge trapping in the substrate.

摘要翻译： 一种用于擦除诸如包括非用户数据或虚拟存储元件的NAND串的非易失性存储器的技术。 非用户数据存储元件的电压通过施加到衬底的擦除电压的受控增加而被电容性耦合。 通过使通路栅极晶体管处于非导通状态来浮置电压，其中通过栅极晶体管位于电压驱动器和非用户数据存储元件之间。 选择栅极晶体管的电压也可以电容耦合得更高。 衬底电压可以逐步增加和/或作为连续斜坡增加。 在一种方法中，外部虚拟存储元件浮动，同时内部虚拟存储元件被驱动。 在另一种方法中，外部和内部虚拟存储元件都浮起来。 由于基板中的电荷捕获减少，存储元件的写擦除耐久性增加。

公开(公告)号：US07436019B2

公开(公告)日：2008-10-14

申请号：US11622634

申请日：2007-01-12

申请人： Jeffrey W. Lutze ,  Tuan Pham ,  Masaaki Higashitani

发明人： Jeffrey W. Lutze ,  Tuan Pham ,  Masaaki Higashitani

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521

摘要： A non-volatile memory array has word lines coupled to floating gates, the floating gates having an upper portion that is adapted to provide increased surface area, and thereby, to provide increased coupling to the word lines. Shielding between floating gates is also provided. The upper portion covers part of a lower portion of the floating gate and leaves a part of the lower portion uncovered. A control gate is coplanar with a top surface of the upper portion, a vertical side of the upper portion, and the uncovered portion of the lower portion.

摘要翻译： 非易失性存储器阵列具有耦合到浮动栅极的字线，浮动栅极具有适于提供增加的表面积的上部部分，从而提供增加的与字线的耦合。 还提供了浮动门之间的屏蔽。 上部覆盖浮动门的下部的一部分并且使下部的未被覆盖的部分离开。 控制栅极与上部的上表面，上部的垂直侧和下部的未覆盖部分共面。

公开(公告)号：US20080248621A1

公开(公告)日：2008-10-09

申请号：US12058512

申请日：2008-03-28

申请人： James Kai ,  Tuan Pham ,  Masaaki Higashitani ,  George Matamis ,  Takashi Orimoto

发明人： James Kai ,  Tuan Pham ,  Masaaki Higashitani ,  George Matamis ,  Takashi Orimoto

IPC分类号： H01L21/336

CPC分类号： H01L27/11529 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/11539

摘要： Non-volatile memory and integrated memory and peripheral circuitry fabrication processes are provided. Sets of charge storage regions, such as NAND strings including multiple non-volatile storage elements, are formed over a semiconductor substrate using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates for the charge storage regions and the gate regions of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions of these devices can be formed from the layer forming the control gates of the memory array.

摘要翻译： 提供非易失性存储器和集成存储器和外围电路制造工艺。 使用诸如第一多晶硅层的电荷存储材料层在半导体衬底上形成诸如包括多个非易失性存储元件的NAND串的电荷存储区的集合。 中间电介质层设置在电荷存储区域的上方。 将诸如第二多晶硅层的导电材料层沉积在衬底上并被蚀刻以形成用于存储元件组的选择晶体管的电荷存储区域和栅极区域的控制栅极。 从衬底的一部分去除第一层多晶硅，便于仅从第二层多晶硅制造选择晶体管栅极区。 外围电路形成也被并入到制造过程中以形成诸如高电压和逻辑晶体管的器件的栅极区域。 这些器件的栅极区域可以由形成存储器阵列的控制栅极的层形成。